On Wed, Mar 26, 2025 at 12:10:59PM +0400, George Moussalem via B4 Relay wrote:
> From: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
>
> Add phy and controller nodes for a 2-lane Gen2 and
> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> one global interrupt.
>
> NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
> Signed-off-by: Sricharan R <quic_srichara@xxxxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> Signed-off-by: George Moussalem <george.moussalem@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 246 +++++++++++++++++++++++++++++++++-
> 1 file changed, 244 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 8914f2ef0bc47fda243b19174f77ce73fc10757d..9f695f0d9c6b7f29c4564977cadd6a78b55a044f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> status = "disabled";
> };
>
> + pcie1_phy: phy@7e000{
> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> + reg = <0x0007e000 0x800>;
> +
> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> +
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + num-lanes = <1>;
> +
> + status = "disabled";
> + };
> +
> + pcie0_phy: phy@86000{
> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> + reg = <0x00086000 0x800>;
> +
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> +
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq5018-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> reg = <0x01800000 0x80000>;
> clocks = <&xo_board_clk>,
> <&sleep_clk>,
> - <0>,
> - <0>,
> + <&pcie0_phy>,
> + <&pcie1_phy>,
> <0>,
> <0>,
> <0>,
> @@ -387,6 +421,214 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + pcie1: pcie@80000000 {
> + compatible = "qcom,pcie-ipq5018";
> + reg = <0x80000000 0xf1d>,
> + <0x80000f20 0xa8>,
> + <0x80001000 0x1000>,
> + <0x00078000 0x3000>,
> + <0x80100000 0x1000>,
> + <0x0007b000 0x1000>;
> + reg-names = "dbi",
> + "elbi",
> + "atu",
> + "parf",
> + "config",
> + "mhi";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + /*
> + * In IPQ5018, the PCIe controller supports gen3,
nit: no need to mention IPQ5018.
- Mani
--
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