Re: [PATCH v6 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes

[Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>]

On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
> On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
> > From: Nitheesh Sekar<quic_nsekar@xxxxxxxxxxx>
> >
> > Add phy and controller nodes for a 2-lane Gen2 and
> Controller is Gen 3 capable but you are limiting it to Gen 2.
>
> > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> > one global interrupt.
> >
> > Signed-off-by: Nitheesh Sekar<quic_nsekar@xxxxxxxxxxx>
> > Signed-off-by: Sricharan R<quic_srichara@xxxxxxxxxxx>
> > Signed-off-by: George Moussalem<george.moussalem@xxxxxxxxxxx>
> One comment below. With that addressed,
>
> Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@xxxxxxxxxx>
>
> > ---
> >   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
> >   1 file changed, 232 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > index 8914f2ef0bc4..d08034b57e80 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> >   			status = "disabled";
> >   		};
> >   
> > +		pcie1_phy: phy@7e000{
> > +			compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > +			reg = <0x0007e000 0x800>;
> > +
> > +			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> > +
> > +			resets = <&gcc GCC_PCIE1_PHY_BCR>,
> > +				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
> > +
> > +			#clock-cells = <0>;
> > +			#phy-cells = <0>;
> > +
> > +			num-lanes = <1>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		pcie0_phy: phy@86000{
> > +			compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > +			reg = <0x00086000 0x800>;
> > +
> > +			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> > +
> > +			resets = <&gcc GCC_PCIE0_PHY_BCR>,
> > +				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
> > +
> > +			#clock-cells = <0>;
> > +			#phy-cells = <0>;
> > +
> > +			num-lanes = <2>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> >   		tlmm: pinctrl@1000000 {
> >   			compatible = "qcom,ipq5018-tlmm";
> >   			reg = <0x01000000 0x300000>;
> > @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> >   			reg = <0x01800000 0x80000>;
> >   			clocks = <&xo_board_clk>,
> >   				 <&sleep_clk>,
> > -				 <0>,
> > -				 <0>,
> > +				 <&pcie0_phy>,
> > +				 <&pcie1_phy>,
> >   				 <0>,
> >   				 <0>,
> >   				 <0>,
> > @@ -387,6 +421,202 @@ frame@b128000 {
> >   				status = "disabled";
> >   			};
> >   		};
> > +
> > +		pcie1: pcie@80000000 {
> > +			compatible = "qcom,pcie-ipq5018";
> > +			reg = <0x80000000 0xf1d>,
> > +			      <0x80000f20 0xa8>,
> > +			      <0x80001000 0x1000>,
> > +			      <0x00078000 0x3000>,
> > +			      <0x80100000 0x1000>,
> > +			      <0x0007b000 0x1000>;
> > +			reg-names = "dbi",
> > +				    "elbi",
> > +				    "atu",
> > +				    "parf",
> > +				    "config",
> > +				    "mhi";
> > +			device_type = "pci";
> > +			linux,pci-domain = <0>;
> > +			bus-range = <0x00 0xff>;
> > +			num-lanes = <1>;
> > +			max-link-speed = <2>;
> This still needs some justification. If Qcom folks didn't reply, atleast move
> this to board dts with a comment saying that the link is not coming up with
> Gen3.
>
> - Mani
The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is 
limited Gen2 and does not supported Gen3.
Hence, it is restricted using the DTSI property.

--
Thanks,
Praveenkumar