From: luyulin <luyulin@xxxxxxxxxxxxxxxxxx> Add document for the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations. Signed-off-by: luyulin <luyulin@xxxxxxxxxxxxxxxxxx> --- .../bindings/ata/eswin,eic7700-ahci.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml diff --git a/Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml b/Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file mode 100644 index 000000000000..9ef58c9c2f28 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC SATA Controller + +maintainers: + - Yulin Lu <luyulin@xxxxxxxxxxxxxxxxxx> + - Huan He <hehuan1@xxxxxxxxxxxxxxxxxx> + +description: + This document defines device tree bindings for the Synopsys DWC + implementation of the AHCI SATA controller found in Eswin's + Eic7700 SoC platform. + +select: + properties: + compatible: + const: eswin,eic7700-ahci + required: + - compatible + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-ahci + - const: snps,dwc-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports-implemented: + const: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: aclk + + resets: + maxItems: 1 + + reset-names: + const: arst + + phys: + maxItems: 1 + + phy-names: + const: sata-phy + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports-implemented + +unevaluatedProperties: false + +examples: + - | + sata@50420000 { + compatible = "eswin,eic7700-ahci", "snps,dwc-ahci"; + reg = <0x50420000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <58>; + ports-implemented = <0x1>; + clocks = <&gate_clk_hsp_cfgclk>, <&gate_clk_hsp_aclk>; + clock-names = "pclk", "aclk"; + resets = <&reset 96>; + reset-names = "arst"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + }; -- 2.25.1
