On 5/16/25 12:14, Edgecombe, Rick P wrote: > Meanwhile I'm watching patches to make 5 level paging walks unconditional fly by > because people couldn't find a cost to the extra level of walk. So re-litigate, > no. But I'll probably remain quietly suspicious of the exact cost/value. At > least on the CPU side, I totally missed the IOTLB side at first, sorry. It's a little more complicated than just the depth of the worst-case walk. In practice, many page walks can use the mid-level paging structure caches because the mappings aren't sparse. With 5-level paging in particular, userspace doesn't actually change much at all. Its layout is pretty much the same unless folks are opting in to the higher (5-level only) address space. So userspace isn't sparse, at least at the scale of what 5-level paging is capable of. For the kernel, things are a bit more spread out than they were before. For instance, the direct map and vmalloc() are in separate p4d pages when they used to be nestled together in the same half of one pgd. But, again, they're not *that* sparse. The direct map, for example, doesn't become more sparse, it just moves to a lower virtual address. Ditto for vmalloc(). Just because 5-level paging has a massive vmalloc() area doesn't mean we use it. Basically, 5-level paging adds a level to the top of the page walk, and we're really good at caching those when they're not accessed sparsely. CPUs are not as good at caching the leaf side of the page walk. There are tricks like AMD's TLB coalescing that help. But, generally, each walk on the leaf end of the walks eats a TLB entry. Those just don't cache as well as the top of the tree. That's why we need to be more maniacal about reducing leaf levels than the levels toward the root.
