AD4030 and similar designs support three different options for the clock
that frames ADC output data. Each option implies a different hardware
configuration for reading ADC data. Document AD4030 clock mode options.
Co-developed-by: Sergiu Cuciurean <sergiu.cuciurean@xxxxxxxxxx>
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@xxxxxxxxxx>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@xxxxxxxxxx>
---
.../devicetree/bindings/iio/adc/adi,ad4030.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
index bee85087a7b2..1e4e025b835f 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
@@ -78,6 +78,18 @@ properties:
interrupt-names:
const: busy
+ adi,clock-mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ spi, echo, host ]
+ default: spi
+ description:
+ Describes how the clock that frames ADC data output is setup.
+ spi - Spi-compatible. Normal SPI operation clocking.
+ echo - Echo-clock. Synchronous clock echoing to ease timing requirements
+ when using isolation on the digital interface.
+ host - Host. The Host clock mode uses an internal oscillator to clock out
+ the data bits. In this mode, the spi controller is not driving SCLK.
+
required:
- compatible
- reg
--
2.39.2
