On 8/29/25 7:44 PM, Marcelo Schmitt wrote: > On echo and host clock modes, AD4030 and similar devices can do two data > bit transitions per clock cycle per active lane. Document how to specify > dual data rate (DDR) feature for AD4030 series devices in device tree. > I don't think this needs to be in the devicetree. Dual data rate doesn't depend on wiring, it only depends on if the SPI controller supports it or not. The core SPI code in Linux already has dtr_caps for SPI controllers to indicate that they have DDR support. So an ADC driver can just check this flag to see if the controller supports it. No devicetree flags required.
