SME adds a number of new system registers, update get-reg-list to check for
them based on the visibility of SME.
Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
---
tools/testing/selftests/kvm/arm64/get-reg-list.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testing/selftests/kvm/arm64/get-reg-list.c
index 011fad95dd02..54b371330f57 100644
--- a/tools/testing/selftests/kvm/arm64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c
@@ -61,7 +61,13 @@ static struct feature_id_reg feat_id_regs[] = {
REG_FEAT(HFGITR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2),
REG_FEAT(HDFGRTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2),
REG_FEAT(HDFGWTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2),
- REG_FEAT(ZCR_EL2, ID_AA64PFR0_EL1, SVE, IMP),
+ REG_FEAT(SMCR_EL1, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(SMCR_EL2, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(SMIDR_EL1, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(SMPRI_EL1, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(SMPRIMAP_EL2, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(TPIDR2_EL0, ID_AA64PFR1_EL1, SME, IMP),
+ REG_FEAT(SVCR, ID_AA64PFR1_EL1, SME, IMP),
REG_FEAT(SCTLR2_EL1, ID_AA64MMFR3_EL1, SCTLRX, IMP),
REG_FEAT(VDISR_EL2, ID_AA64PFR0_EL1, RAS, IMP),
REG_FEAT(VSESR_EL2, ID_AA64PFR0_EL1, RAS, IMP),
@@ -351,6 +357,7 @@ static __u64 base_regs[] = {
ARM64_SYS_REG(3, 0, 0, 0, 0), /* MIDR_EL1 */
ARM64_SYS_REG(3, 0, 0, 0, 6), /* REVIDR_EL1 */
ARM64_SYS_REG(3, 1, 0, 0, 1), /* CLIDR_EL1 */
+ ARM64_SYS_REG(3, 1, 0, 0, 6), /* SMIDR_EL1 */
ARM64_SYS_REG(3, 1, 0, 0, 7), /* AIDR_EL1 */
ARM64_SYS_REG(3, 3, 0, 0, 1), /* CTR_EL0 */
ARM64_SYS_REG(2, 0, 0, 0, 4),
@@ -482,6 +489,8 @@ static __u64 base_regs[] = {
ARM64_SYS_REG(3, 0, 1, 0, 1), /* ACTLR_EL1 */
ARM64_SYS_REG(3, 0, 1, 0, 2), /* CPACR_EL1 */
KVM_ARM64_SYS_REG(SYS_SCTLR2_EL1),
+ ARM64_SYS_REG(3, 0, 1, 2, 4), /* SMPRI_EL1 */
+ ARM64_SYS_REG(3, 0, 1, 2, 6), /* SMCR_EL1 */
ARM64_SYS_REG(3, 0, 2, 0, 0), /* TTBR0_EL1 */
ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */
ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */
@@ -502,9 +511,11 @@ static __u64 base_regs[] = {
ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */
ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */
ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */
+ ARM64_SYS_REG(3, 3, 4, 2, 2), /* SVCR */
ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */
ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */
ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */
+ ARM64_SYS_REG(3, 3, 13, 0, 5), /* TPIDR2_EL0 */
ARM64_SYS_REG(3, 3, 14, 0, 1), /* CNTPCT_EL0 */
ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */
ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */
@@ -713,6 +724,8 @@ static __u64 el2_regs[] = {
SYS_REG(HFGITR_EL2),
SYS_REG(HACR_EL2),
SYS_REG(ZCR_EL2),
+ SYS_REG(SMPRIMAP_EL2),
+ SYS_REG(SMCR_EL2),
SYS_REG(HCRX_EL2),
SYS_REG(TTBR0_EL2),
SYS_REG(TTBR1_EL2),
--
2.39.5
