On Mon, Sep 01, 2025 at 10:52:38AM +0530, Manali Shukla wrote: > From: Santosh Shukla <santosh.shukla@xxxxxxx> > > The local interrupts are extended to include more LVT registers in > order to allow additional interrupt sources, like Instruction Based > Sampling (IBS) and many more. > > Currently there are four additional LVT registers defined and they are > located at APIC offsets 400h-530h. > > AMD IBS driver is designed to use EXTLVT (Extended interrupt local > vector table) by default for driver initialization. > > Extended LVT registers are required to be emulated to initialize the > guest IBS driver successfully. > > Please refer to Section 16.4.5 in AMD Programmer's Manual Volume 2 at > https://bugzilla.kernel.org/attachment.cgi?id=306250 for more details > on Extended LVT. > > Signed-off-by: Santosh Shukla <santosh.shukla@xxxxxxx> > Co-developed-by: Manali Shukla <manali.shukla@xxxxxxx> > Signed-off-by: Manali Shukla <manali.shukla@xxxxxxx> > --- > arch/x86/include/asm/apicdef.h | 17 ++++++++++++++ > arch/x86/kvm/cpuid.c | 6 +++++ > arch/x86/kvm/lapic.c | 42 ++++++++++++++++++++++++++++++++++ > arch/x86/kvm/lapic.h | 1 + > arch/x86/kvm/svm/avic.c | 4 ++++ > arch/x86/kvm/svm/svm.c | 6 +++++ > 6 files changed, 76 insertions(+) > <snip> > diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c > index a34c5c3b164e..1b46de10e328 100644 > --- a/arch/x86/kvm/svm/avic.c > +++ b/arch/x86/kvm/svm/avic.c > @@ -669,6 +669,10 @@ static bool is_avic_unaccelerated_access_trap(u32 offset) > case APIC_LVTERR: > case APIC_TMICT: > case APIC_TDCR: > + case APIC_EILVTn(0): > + case APIC_EILVTn(1): > + case APIC_EILVTn(2): > + case APIC_EILVTn(3): This should actually be conditional on X86_FEATURE_EXTLVT. I also forgot to add for the previous patch: the feature name needs to be changed to reflect the true nature of the feature bit. - Naveen
