Hello:
This patch was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@xxxxxxxxxxxxx>:
On Wed, 16 Jul 2025 18:07:45 +0530 you wrote:
> When injecting IPIs to a set of harts, the IMSIC IPI support will do
> a separate MMIO write to the SETIPNUM_LE register of each target hart.
> This means on a platform where IMSIC is trap-n-emulated, there will be
> N MMIO traps when injecting IPI to N target harts hence IMSIC IPIs will
> be slow on such platform compared to the SBI IPI extension.
>
> Unfortunately, there is no DT, ACPI, or any other way of discovering
> whether the underlying IMSIC is trap-n-emulated. Using MMIO write to
> the SETIPNUM_LE register for injecting IPI is purely a software choice
> in the IMSIC driver hence add a kernel parameter to allow users disable
> IMSIC IPIs on platforms with trap-n-emulated IMSIC.
>
> [...]
Here is the summary with links:
- [v4] irqchip/riscv-imsic: Add kernel parameter to disable IPIs
https://git.kernel.org/riscv/c/ea92b6046d35
You are awesome, thank you!
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