Hi Babu, On 7/25/25 11:29 AM, Babu Moger wrote: > ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. > Bits Description > 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth > Monitoring Counter ID + 1 > > The feature details are documented in APM listed below [1]. > [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming > Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth > Monitoring (ABMC). > > Detect the feature and number of assignable counters supported. For > backward compatibility, upon detecting the assignable counter feature, > enable the mbm_total_bytes and mbm_local_bytes events that users are > familiar with as part of original L3 MBM support. > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> > --- ... > diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c > index 267e9206a999..09cb5a70b1cb 100644 > --- a/arch/x86/kernel/cpu/resctrl/core.c > +++ b/arch/x86/kernel/cpu/resctrl/core.c > @@ -883,6 +883,8 @@ static __init bool get_rdt_mon_resources(void) > resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID); > ret = true; > } > + if (rdt_cpu_has(X86_FEATURE_ABMC)) > + ret = true; > > if (!ret) > return false; > @@ -990,7 +992,8 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) > To complement the change below, shouldn't the snippet that precedes it look like: if (!cpu_has(c, X86_FEATURE_CQM_LLC) && !cpu_has(c, X86_FEATURE_ABMC)) { ... return; } > if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || > cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || > - cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { > + cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL) || > + cpu_has(c, X86_FEATURE_ABMC)) { > u32 eax, ebx, ecx, edx; > > /* QoS sub-leaf, EAX=0Fh, ECX=1 */ > diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c > index 2558b1bdef8b..0a695ce68f46 100644 > --- a/arch/x86/kernel/cpu/resctrl/monitor.c > +++ b/arch/x86/kernel/cpu/resctrl/monitor.c > @@ -339,6 +339,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) > unsigned int mbm_offset = boot_cpu_data.x86_cache_mbm_width_offset; > struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); > unsigned int threshold; > + u32 eax, ebx, ecx, edx; > > snc_nodes_per_l3_cache = snc_get_config(); > > @@ -368,14 +369,18 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) > */ > resctrl_rmid_realloc_threshold = resctrl_arch_round_mon_val(threshold); > > - if (rdt_cpu_has(X86_FEATURE_BMEC)) { > - u32 eax, ebx, ecx, edx; > - > + if (rdt_cpu_has(X86_FEATURE_BMEC) || rdt_cpu_has(X86_FEATURE_ABMC)) { > /* Detect list of bandwidth sources that can be tracked */ > cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); > r->mon.mbm_cfg_mask = ecx & MAX_EVT_CONFIG_BITS; I interpret this mbm_cfg_mask initialization that an ABMC system will report which of the memory transactions can be monitored. In patch #15 "fs/resctrl: Introduce event configuration field in struct mon_evt" the event configurations of memory transactions that should be monitored are hardcoded as below without taking into account what the system supports: resctrl_mon_resource_init() { ... mon_event_all[QOS_L3_MBM_TOTAL_EVENT_ID].evt_cfg = MAX_EVT_CONFIG_BITS; mon_event_all[QOS_L3_MBM_LOCAL_EVENT_ID].evt_cfg = READS_TO_LOCAL_MEM | READS_TO_LOCAL_S_MEM | NON_TEMP_WRITE_TO_LOCAL_MEM; ... } It may thus be that a system may not support all memory transactions it is configured to monitor. It seems to me that the initialization done in resctrl_mon_resource_init() needs to take r->mon.mbm_cfg_mask (what the system supports) into account? If so, then the same hardcoding done by patch #32 in resctrl_mbm_assign_mode_write() should also be changed. Reinette
