From: Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx> Add xmipsexectl instruction opcodes. This includes the MIPS.PAUSE, MIPS.EHB, and MIPS.IHB instructions. Signed-off-by: Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx> Reviewed-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> --- arch/riscv/include/asm/vendor_extensions/mips.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h index 133e55985d827ce7d6057004b590bdcbbdb1ec8c..ea8ca747d691df2e9ee7e5360f800fbdccfe3945 100644 --- a/arch/riscv/include/asm/vendor_extensions/mips.h +++ b/arch/riscv/include/asm/vendor_extensions/mips.h @@ -15,4 +15,23 @@ struct riscv_isa_vendor_ext_data_list; extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips; #endif +/* Extension specific instructions */ + +/* + * All of the xmipsexectl extension instructions are + * ‘hint’ encodings of the SLLI instruction, + * with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB, + * and imm = 5 for PAUSE. + * MIPS.PAUSE is an alternative opcode which is implemented to have the + * same behavior as PAUSE on some MIPS RISCV cores. + * MIPS.EHB clears all execution hazards before allowing + * any subsequent instructions to execute. + * MIPS.IHB clears all instruction hazards before + * allowing any subsequent instructions to fetch. + */ + +#define MIPS_PAUSE ".4byte 0x00501013\n\t" +#define MIPS_EHB ".4byte 0x00301013\n\t" +#define MIPS_IHB ".4byte 0x00101013\n\t" + #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H -- 2.34.1
