This patch series introduces the DDR Performance Monitor (DDRPERFM) support for
STM32MP platforms.
The series firstly improves the STM32MP25 RCC driver to make it usable
as an access controller, needed for driver probe.
It also includes the addition of device tree bindings, the HDP driver,
documentation and updates to the device tree files for
STM32MP13, STM32MP15 and STM32MP25 SoCs.
The series also updates the MAINTAINERS file to include myself as the
maintainer for the STM32 DDR PMU driver.
Signed-off-by: Clément Le Goffic <clement.legoffic@xxxxxxxxxxx>
---
Changes in v2:
- MAINTAINERS:
Due to reorganisation, my contract with ST ends at the end of this month
and I will no longer have access to this mailbox.
Therefore, I will be available for any mission related to embedded and
kernel linux.
Change email address in MAINTAINERS file for STM32 DDR PMU driver.
- devicetrees:
-stm32mp257f-dk: add LPDDR4 channel
-stm32mp257f-ev1: add DDR4 channel
- dt-bindings:
- perf:
- Change Maintainer email address
- Drop obvious descriptions (clocks and reset property)
- Drop redundant "bindings" in commit message
- Drop unneedded "stm32mp151-ddr-pmu" compatible
- s/st,dram-type/memory-channel/, memory-channel property is not in
dtschema library so it will produce an error in the v2.
- rcc:
- Add required "access-controller-cells" property in example
- ddr-channel:
- Add bindings as per jedec,lpddrX-channel bindings
- driver:
- Substitute the parsing of the 'st,dram-type' vendor devicetree
property value with the parsing of the [lp]ddr channel compatible
- Remove unneeded "stm32mp151-ddr-pmu" compatible
- Use dev_err_probe when possible
- Assert and deassert reset line unconditionnaly
- Use `devm_reset_control_get_optional_exclusive` instead of
`of_property_present` then `devm_reset_control_get`
- Use `devm_clk_get_optional_prepared` instead of `of_property_present`
then `devm_clk_get_prepared`
- Disable and unprepare the clock at end of probe
- Add io.h include as per LKP test report
- Removed `of_match_ptr` reference in `platform_driver` struct
- Add `pm_sleep_ptr` macro for `platform_driver` struct's `pm` field
- Link to v1: https://lore.kernel.org/r/20250623-ddrperfm-upstream-v1-0-7dffff168090@xxxxxxxxxxx
---
Clément Le Goffic (16):
bus: firewall: move stm32_firewall header file in include folder
dt-bindings: stm32: stm32mp25: add `access-controller-cell` property
clk: stm32mp25: add firewall grant_access ops
arm64: dts: st: set rcc as an access-controller
dt-bindings: memory: add jedec,ddr[3-4]-channel binding
arm64: dts: st: add LPDDR channel to stm32mp257f-dk board
arm64: dts: st: add DDR channel to stm32mp257f-ev1 board
dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings
perf: stm32: introduce DDRPERFM driver
Documentation: perf: stm32: add ddrperfm support
MAINTAINERS: add myself as STM32 DDR PMU maintainer
ARM: dts: stm32: add ddrperfm on stm32mp131
ARM: dts: stm32: add ddrperfm on stm32mp151
arm64: dts: st: add ddrperfm on stm32mp251
arm64: dts: st: support ddrperfm on stm32mp257f-dk
arm64: dts: st: support ddrperfm on stm32mp257f-ev1
Documentation/admin-guide/perf/index.rst | 1 +
Documentation/admin-guide/perf/stm32-ddr-pmu.rst | 86 ++
.../bindings/clock/st,stm32mp25-rcc.yaml | 7 +
.../memory-controllers/ddr/jedec,ddr-channel.yaml | 53 ++
.../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 87 ++
MAINTAINERS | 7 +
arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +
arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 12 +
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 10 +
drivers/bus/stm32_etzpc.c | 3 +-
drivers/bus/stm32_firewall.c | 3 +-
drivers/bus/stm32_rifsc.c | 3 +-
drivers/clk/stm32/clk-stm32mp25.c | 40 +-
drivers/perf/Kconfig | 11 +
drivers/perf/Makefile | 1 +
drivers/perf/stm32_ddr_pmu.c | 910 +++++++++++++++++++++
{drivers => include/linux}/bus/stm32_firewall.h | 0
19 files changed, 1249 insertions(+), 7 deletions(-)
---
base-commit: d7b8f8e20813f0179d8ef519541a3527e7661d3a
change-id: 20250526-ddrperfm-upstream-bf07f57775da
Best regards,
--
Clément Le Goffic <clement.legoffic@xxxxxxxxxxx>
