On Tuesday, July 1, 2025 3:17:47 PM Central European Summer Time Jonathan Cameron wrote:
> On Mon, 23 Jun 2025 17:29:02 +0200
> "Fabio M. De Francesco" <fabio.m.de.francesco@xxxxxxxxxxxxxxx> wrote:
>
> > Add documentation on how to resolve conflicts between CXL Fixed Memory
> > Windows, Platform Memory Holes, and Endpoint Decoders.
> >
> > Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@xxxxxxxxxxxxxxx>
> > ---
> >
> > v2 -> v3: Rework a few phrases for better clarity.
> > Fix grammar and syntactic errors (Randy, Alok).
> > Fix semantic errors ("size does not comply", Alok).
> > Fix technical errors ("decoder's total memory?", Alok).
> >
> > v1 -> v2: Rewrite "Summary of the Change" section, 3r paragraph.
> >
> > Documentation/driver-api/cxl/conventions.rst | 85 ++++++++++++++++++++
> > 1 file changed, 85 insertions(+)
> >
> > diff --git a/Documentation/driver-api/cxl/conventions.rst b/Documentation/driver-api/cxl/conventions.rst
> > index da347a81a237..d6c8f4cf2f5b 100644
> > --- a/Documentation/driver-api/cxl/conventions.rst
> > +++ b/Documentation/driver-api/cxl/conventions.rst
> > @@ -45,3 +45,88 @@ Detailed Description of the Change
> > ----------------------------------
> >
> > <Propose spec language that corrects the conflict.>
> > +
> > +
> > +Resolve conflict between CFMWS, Platform Memory Holes, and Endpoint Decoders
> > +============================================================================
> > +
> > +Document
> > +--------
> > +
> > +CXL Revision 3.2, Version 1.0
> > +
> > +License
> > +-------
> > +
> > +SPDX-License Identifier: CC-BY-4.0
> > +
> > +Creator/Contributors
> > +--------------------
> > +
> > +Fabio M. De Francesco, Intel
> > +Dan J. Williams, Intel
> > +Mahesh Natu, Intel
> > +
> > +Summary of the Change
> > +---------------------
> > +
> > +According to the current CXL Specifications (Revision 3.2, Version 1.0)
> > +the CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host
> > +Physical Address (HPA) windows that are associated with each CXL Host
> > +Bridge. Each window represents a contiguous HPA range that may be
> > +interleaved across one or more targets, some of which are CXL Host Bridges.
> > +Associated with each window is a set of restrictions that govern its usage.
> > +It is the OSPM’s responsibility to utilize each window for the specified
> > +use.
> > +
> > +Table 9-22 states the Window Size field contains the total number of
> > +consecutive bytes of HPA this window represents and this value shall be a
> > +multiple of Number of Interleave Ways * 256 MB.
> > +
> > +Platform Firmware (BIOS) might reserve part of physical addresses below
> > +4 GB (e.g., the Low Memory Hole that describes PCIe memory space for MMIO
> > +or a requirement for the greater than 8 way interleave CXL regions starting
> > +at address 0). In that case the Window Size value cannot be anymore
> > +constrained to the NIW * 256 MB above-mentioned rule.
>
> I'm not following argument for large interleave at address 0 being a problem
> (if we ignore the low memory hole and similar as a separate issue).
>
> Even
> if it is the interaction with the low memory hole, is 12 way interleave
> of 256MiB devices a problem? Fills up to 3GiB.
>
Right, I'll drop that argument for large interleaves. The problem is still the
MMIO hole that might intersect the 3 GiB requirement for 12 way interleave.
Thanks,
Fabio
