From: Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx>
Use the hwprobe syscall to decide which PAUSE instruction to execute in
userspace code.
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx>
---
tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
--- a/tools/arch/riscv/include/asm/vdso/processor.h
+++ b/tools/arch/riscv/include/asm/vdso/processor.h
@@ -4,26 +4,33 @@
#ifndef __ASSEMBLY__
+#include <asm/hwprobe.h>
+#include <sys/hwprobe.h>
+#include <asm/vendor/mips.h>
#include <asm-generic/barrier.h>
static inline void cpu_relax(void)
{
+ struct riscv_hwprobe pair;
+ bool has_mipspause;
#ifdef __riscv_muldiv
int dummy;
/* In lieu of a halt instruction, induce a long-latency stall. */
__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
#endif
-#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
- /*
- * Reduce instruction retirement.
- * This assumes the PC changes.
- */
- __asm__ __volatile__ ("pause");
-#else
- /* Encoding of the pause instruction */
- __asm__ __volatile__ (".4byte 0x100000F");
-#endif
+ pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
+ __riscv_hwprobe(&pair, 1, 0, NULL, 0);
+ has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
+
+ if (has_mipspause) {
+ /* Encoding of the mips pause instruction */
+ __asm__ __volatile__(".4byte 0x00501013");
+ } else {
+ /* Encoding of the pause instruction */
+ __asm__ __volatile__(".4byte 0x100000F");
+ }
+
barrier();
}
--
2.34.1
