On Fri, Jun 20, 2025 at 10:13:03PM +0000, Colton Lewis wrote:
> Add a cpucap for FEAT_PMUv3_PMICNTR, meaning there is a dedicated
> instruction counter as well as the cycle counter.
>
> Signed-off-by: Colton Lewis <coltonlewis@xxxxxxxxxx>
I don't see this capability being used in this series.
Thanks,
Oliver
> ---
> arch/arm64/kernel/cpufeature.c | 7 +++++++
> arch/arm64/tools/cpucaps | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 278294fdc97d..85dea9714928 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2904,6 +2904,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> .matches = has_cpuid_feature,
> ARM64_CPUID_FIELDS(ID_AA64DFR0_EL1, HPMN0, IMP)
> },
> + {
> + .desc = "PMU Dedicated Instruction Counter",
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .capability = ARM64_HAS_PMICNTR,
> + .matches = has_cpuid_feature,
> + ARM64_CPUID_FIELDS(ID_AA64DFR1_EL1, PMICNTR, IMP)
> + },
> #ifdef CONFIG_ARM64_SME
> {
> .desc = "Scalable Matrix Extension",
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 5b196ba21629..6dd72fcdd612 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -47,6 +47,7 @@ HAS_LSE_ATOMICS
> HAS_MOPS
> HAS_NESTED_VIRT
> HAS_PAN
> +HAS_PMICNTR
> HAS_PMUV3
> HAS_S1PIE
> HAS_S1POE
> --
> 2.50.0.714.g196bf9f422-goog
>
