Hi Reinette,
On 6/17/25 22:45, Reinette Chatre wrote:
> Hi Babu,
>
> Please modify subject prefix to "x86,fs/resctrl" since this adds new arch
> API called by resctrl fs.
Sure.
>
> On 6/11/25 2:23 PM, Babu Moger wrote:
>> Smart Data Cache Injection (SDCI) is a mechanism that enables direct
>> insertion of data from I/O devices into the L3 cache. It can the demands
>
> "It can the demands" -> "It can reduce demands"?
Sure.
>
>> on DRAM bandwidth and reduces latency to the processor consuming the I/O
>> data.
>>
>> Introduce cache resource property "io_alloc_capable" that an architecture
>> can set if a portion of the L3 cache can be allocated for I/O traffic.
>
> I think "L3" should be dropped because the cache resource property is not
> unique to L3. It is a property of all cache resources.
>
>> Set this property on x86 systems that support SDCIAE (L3 Smart Data Cache
>> Injection Allocation Enforcement).
>
> Here it can be mentioned that this property is only set for the L3 cache
> resource on systems that supports SDCIAE.
>
>>
>> Signed-off-by: Babu Moger <babu.moger@xxxxxxx>
>> ---
>> v6: No changes.
>>
>> v5: No changes.
>>
>> v4: Updated the commit message and code comment based on feedback.
>>
>> v3: Rewrote commit log. Changed the text to bit generic than the AMD specific.
>> Renamed the rdt_get_sdciae_alloc_cfg() to rdt_set_io_alloc_capable().
>> Removed leftover comment from v2.
>>
>> v2: Changed sdciae_capable to io_alloc_capable to make it generic feature.
>> Also moved the io_alloc_capable in struct resctrl_cache.
>> ---
>> arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++
>> include/linux/resctrl.h | 3 +++
>> 2 files changed, 10 insertions(+)
>>
>> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
>> index 326c679ade5c..a3d174362249 100644
>> --- a/arch/x86/kernel/cpu/resctrl/core.c
>> +++ b/arch/x86/kernel/cpu/resctrl/core.c
>> @@ -274,6 +274,11 @@ static void rdt_get_cdp_config(int level)
>> rdt_resources_all[level].r_resctrl.cdp_capable = true;
>> }
>>
>> +static void rdt_set_io_alloc_capable(struct rdt_resource *r)
>> +{
>> + r->cache.io_alloc_capable = true;
>> +}
>> +
>> static void rdt_get_cdp_l3_config(void)
>> {
>> rdt_get_cdp_config(RDT_RESOURCE_L3);
>> @@ -840,6 +845,8 @@ static __init bool get_rdt_alloc_resources(void)
>> rdt_get_cache_alloc_cfg(1, r);
>> if (rdt_cpu_has(X86_FEATURE_CDP_L3))
>> rdt_get_cdp_l3_config();
>> + if (rdt_cpu_has(X86_FEATURE_SDCIAE))
>> + rdt_set_io_alloc_capable(r);
>> ret = true;
>> }
>> if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
>> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
>> index 9ba771f2ddea..0e8641e41100 100644
>> --- a/include/linux/resctrl.h
>> +++ b/include/linux/resctrl.h
>> @@ -191,6 +191,8 @@ struct rdt_mon_domain {
>> * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid.
>> * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
>> * level has CPU scope.
>> + * @io_alloc_capable: True if portion of the cache can be allocated
>> + * for I/O traffic.
>
> Reading this again I think the description can be improved since technically
> resctrl does not allocate a portion of cache but instead configures the
> portion of cache that device can allocate into.
> So perhaps this can be: "True if portion of the cache can be configured
> for I/O traffic allocation."
Sure.
>
>> */
>> struct resctrl_cache {
>> unsigned int cbm_len;
>> @@ -198,6 +200,7 @@ struct resctrl_cache {
>> unsigned int shareable_bits;
>> bool arch_has_sparse_bitmasks;
>> bool arch_has_per_cpu_cfg;
>> + bool io_alloc_capable;
>> };
>>
>> /**
>
> Reinette
>
--
Thanks
Babu Moger
