Add support for Microchip Azurite DPLL/PTP/SyncE chip family that provides DPLL and PTP functionality. This series bring first part that adds the core functionality and basic DPLL support. The next part of the series will bring additional DPLL functionality like eSync support, phase offset and frequency offset reporting and phase adjustments. Testing was done by myself and by Prathosh Satish on Microchip EDS2 development board with ZL30732 DPLL chip connected over I2C bus. --- Changelog: v10: Usage of str_enabled_disabled() where possible. v9: After discussion with Jakub Kicinski we agreed that it would be better to implement whole functionality in a single driver without touching MFD sub-system. Besides touching multiple sub-systems by single device there are also some technical issues that are easier resolvable in a single driver. Additionally the firmware flashing functionality would bring more than 1000 lines of code with previous approach to the MFD driver - it is not something the MFD maintainers would like to see. Ivan Vecera (14): dt-bindings: dpll: Add DPLL device and pin dt-bindings: dpll: Add support for Microchip Azurite chip family dpll: Add basic Microchip ZL3073x support dpll: zl3073x: Add support for devlink device info dpll: zl3073x: Protect operations requiring multiple register accesses dpll: zl3073x: Fetch invariants during probe dpll: zl3073x: Add clock_id field dpll: zl3073x: Read DPLL types and pin properties from system firmware dpll: zl3073x: Register DPLL devices and pins dpll: zl3073x: Implement input pin selection in manual mode dpll: zl3073x: Add support to get/set priority on input pins dpll: zl3073x: Implement input pin state setting in automatic mode dpll: zl3073x: Add support to get/set frequency on input pins dpll: zl3073x: Add support to get/set frequency on output pins .../devicetree/bindings/dpll/dpll-device.yaml | 76 + .../devicetree/bindings/dpll/dpll-pin.yaml | 45 + .../bindings/dpll/microchip,zl30731.yaml | 115 ++ Documentation/networking/devlink/index.rst | 1 + Documentation/networking/devlink/zl3073x.rst | 37 + MAINTAINERS | 10 + drivers/Kconfig | 4 +- drivers/dpll/Kconfig | 6 + drivers/dpll/Makefile | 2 + drivers/dpll/zl3073x/Kconfig | 36 + drivers/dpll/zl3073x/Makefile | 10 + drivers/dpll/zl3073x/core.c | 967 +++++++++++ drivers/dpll/zl3073x/core.h | 371 ++++ drivers/dpll/zl3073x/dpll.c | 1494 +++++++++++++++++ drivers/dpll/zl3073x/dpll.h | 42 + drivers/dpll/zl3073x/i2c.c | 95 ++ drivers/dpll/zl3073x/prop.c | 358 ++++ drivers/dpll/zl3073x/prop.h | 34 + drivers/dpll/zl3073x/regs.h | 206 +++ drivers/dpll/zl3073x/spi.c | 95 ++ 20 files changed, 4002 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml create mode 100644 Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml create mode 100644 Documentation/networking/devlink/zl3073x.rst create mode 100644 drivers/dpll/zl3073x/Kconfig create mode 100644 drivers/dpll/zl3073x/Makefile create mode 100644 drivers/dpll/zl3073x/core.c create mode 100644 drivers/dpll/zl3073x/core.h create mode 100644 drivers/dpll/zl3073x/dpll.c create mode 100644 drivers/dpll/zl3073x/dpll.h create mode 100644 drivers/dpll/zl3073x/i2c.c create mode 100644 drivers/dpll/zl3073x/prop.c create mode 100644 drivers/dpll/zl3073x/prop.h create mode 100644 drivers/dpll/zl3073x/regs.h create mode 100644 drivers/dpll/zl3073x/spi.c -- 2.49.0
