On 05/06/25 4:19 PM, James Clark wrote: > FEAT_SPEv1p4 (optional from Armv8.8) adds some new filter bits, so > remove them from the previous version's RES0 bits using > PMSEVFR_EL1_RES0_V1P4_EXCL. It also makes some previously available bits > unavailable again, so add those back using PMSEVFR_EL1_RES0_V1P4_INCL. Just wondering - why cannot all the new applicable filter bits be added explicitly for PMSEVFR_EL1_RES0_V1P4 without using exclude and include intermediaries. > E.g: > > E[30], bit [30] > When FEAT_SPEv1p4 is _not_ implemented ... > > FEAT_SPE_V1P3 has the same filters as V1P2 so explicitly add it to the > switch. A small nit - should FEAT_SPE_V1P3 addition be done in a previous patch as it is an already existing thing ? > > Reviewed-by: Leo Yan <leo.yan@xxxxxxx> > Tested-by: Leo Yan <leo.yan@xxxxxxx> > Signed-off-by: James Clark <james.clark@xxxxxxxxxx> > --- > arch/arm64/include/asm/sysreg.h | 7 +++++++ > drivers/perf/arm_spe_pmu.c | 5 ++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index f1bb0d10c39a..880090df3efc 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -358,6 +358,13 @@ > (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) > #define PMSEVFR_EL1_RES0_V1P2 \ > (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) > +#define PMSEVFR_EL1_RES0_V1P4_EXCL \ > + (BIT_ULL(2) | BIT_ULL(4) | GENMASK_ULL(10, 8) | GENMASK_ULL(23, 19)) > +#define PMSEVFR_EL1_RES0_V1P4_INCL \ > + (GENMASK_ULL(31, 26))> +#define PMSEVFR_EL1_RES0_V1P4 \ > + (PMSEVFR_EL1_RES0_V1P4_INCL | \ > + (PMSEVFR_EL1_RES0_V1P2 & ~PMSEVFR_EL1_RES0_V1P4_EXCL)) > > /* Buffer error reporting */ > #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index 3efed8839a4e..d9f6d229dce8 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -701,9 +701,12 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) > case ID_AA64DFR0_EL1_PMSVer_V1P1: > return PMSEVFR_EL1_RES0_V1P1; > case ID_AA64DFR0_EL1_PMSVer_V1P2: > + case ID_AA64DFR0_EL1_PMSVer_V1P3: > + return PMSEVFR_EL1_RES0_V1P2; > + case ID_AA64DFR0_EL1_PMSVer_V1P4: > /* Return the highest version we support in default */ > default: > - return PMSEVFR_EL1_RES0_V1P2; > + return PMSEVFR_EL1_RES0_V1P4; > } > } > >
