I really appreciate your review, thanks a lot!
On 09-06-2025 16:28, Jonathan Cameron wrote:
These changes improve readability and accuracy of the documentation.
Signed-off-by: Alok Tiwari<alok.a.tiwari@xxxxxxxxxx>
One additional comment given you are touching this text.
Reviewed-by: Jonathan Cameron<jonathan.cameron@xxxxxxxxxx>
---
Documentation/driver-api/cxl/memory-devices.rst | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index d732c42526df..e9e2952a967d 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -29,8 +29,8 @@ Platform firmware enumerates a menu of interleave options at the "CXL root port"
(Linux term for the top of the CXL decode topology). From there, PCIe topology
dictates which endpoints can participate in which Host Bridge decode regimes.
Each PCIe Switch in the path between the root and an endpoint introduces a point
-at which the interleave can be split. For example platform firmware may say at a
-given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
+at which the interleave can be split. For example, platform firmware may say at a
Should probably be "platform firmware may say that a given range"
"We addressed these parts based on Gregory Price's comments and
submitted version 2 of the patch."
use phrase -> "platform firmware may say a given range only"
+given range only decodes to one Host Bridge, but that Host Bridge may in turn
interleave cycles across multiple Root Ports. An intervening Switch between a
port and an endpoint may interleave cycles across multiple Downstream Switch
Ports, etc.
@@ -187,7 +187,7 @@ decodes them to "ports", "ports" decode to "endpoints", and "endpoints"
represent the decode from SPA (System Physical Address) to DPA (Device Physical
Address).
Thanks,
Alok
