Hi,
On Sun, May 25, 2025 at 2:22 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote:
>
> On Fri, 23 May 2025 22:35:15 +0000
> Lothar Rubusch <l.rubusch@xxxxxxxxx> wrote:
>
> > Setup regmap cache to cache register configuration. This is a preparatory
> > step for follow up patches, to allow easy acces to the cached
> > configuration.
>
> I think this stands on it's own given registers like the calibbias
> are already both written and read from. So I'd generalize the justification
> to simply reducing unnecessary bus traffic.
>
I (think I) need regmap cache especially for activity / inactivity.
For instance, using cached settings should make it easier to verify
what was enabled when evaluating incomming interrupts. I will rework
the commit message here.
Best,
L
> Jonathan
>
> >
> > Signed-off-by: Lothar Rubusch <l.rubusch@xxxxxxxxx>
> > ---
> > drivers/iio/accel/adxl313.h | 2 ++
> > drivers/iio/accel/adxl313_core.c | 17 +++++++++++++++++
> > drivers/iio/accel/adxl313_i2c.c | 6 ++++++
> > drivers/iio/accel/adxl313_spi.c | 6 ++++++
> > 4 files changed, 31 insertions(+)
> >
> > diff --git a/drivers/iio/accel/adxl313.h b/drivers/iio/accel/adxl313.h
> > index 72f624af4686..fc937bdf83b6 100644
> > --- a/drivers/iio/accel/adxl313.h
> > +++ b/drivers/iio/accel/adxl313.h
> > @@ -54,6 +54,8 @@ extern const struct regmap_access_table adxl312_writable_regs_table;
> > extern const struct regmap_access_table adxl313_writable_regs_table;
> > extern const struct regmap_access_table adxl314_writable_regs_table;
> >
> > +bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg);
> > +
> > enum adxl313_device_type {
> > ADXL312,
> > ADXL313,
> > diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_core.c
> > index 06a771bb4726..0c893c286017 100644
> > --- a/drivers/iio/accel/adxl313_core.c
> > +++ b/drivers/iio/accel/adxl313_core.c
> > @@ -46,6 +46,23 @@ const struct regmap_access_table adxl314_readable_regs_table = {
> > };
> > EXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, IIO_ADXL313);
> >
> > +bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg)
> > +{
> > + switch (reg) {
> > + case ADXL313_REG_DATA_AXIS(0):
> > + case ADXL313_REG_DATA_AXIS(1):
> > + case ADXL313_REG_DATA_AXIS(2):
> > + case ADXL313_REG_DATA_AXIS(3):
> > + case ADXL313_REG_DATA_AXIS(4):
> > + case ADXL313_REG_DATA_AXIS(5):
> > + case ADXL313_REG_FIFO_STATUS:
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +EXPORT_SYMBOL_NS_GPL(adxl313_is_volatile_reg, "IIO_ADXL313");
> > +
> > static int adxl312_check_id(struct device *dev,
> > struct adxl313_data *data)
> > {
> > diff --git a/drivers/iio/accel/adxl313_i2c.c b/drivers/iio/accel/adxl313_i2c.c
> > index a4cf0cf2c5aa..e8636e8ab14f 100644
> > --- a/drivers/iio/accel/adxl313_i2c.c
> > +++ b/drivers/iio/accel/adxl313_i2c.c
> > @@ -21,6 +21,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
> > .rd_table = &adxl312_readable_regs_table,
> > .wr_table = &adxl312_writable_regs_table,
> > .max_register = 0x39,
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > [ADXL313] = {
> > .reg_bits = 8,
> > @@ -28,6 +30,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
> > .rd_table = &adxl313_readable_regs_table,
> > .wr_table = &adxl313_writable_regs_table,
> > .max_register = 0x39,
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > [ADXL314] = {
> > .reg_bits = 8,
> > @@ -35,6 +39,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
> > .rd_table = &adxl314_readable_regs_table,
> > .wr_table = &adxl314_writable_regs_table,
> > .max_register = 0x39,
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > };
> >
> > diff --git a/drivers/iio/accel/adxl313_spi.c b/drivers/iio/accel/adxl313_spi.c
> > index 9a16b40bff34..68e323e81aeb 100644
> > --- a/drivers/iio/accel/adxl313_spi.c
> > +++ b/drivers/iio/accel/adxl313_spi.c
> > @@ -24,6 +24,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
> > .max_register = 0x39,
> > /* Setting bits 7 and 6 enables multiple-byte read */
> > .read_flag_mask = BIT(7) | BIT(6),
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > [ADXL313] = {
> > .reg_bits = 8,
> > @@ -33,6 +35,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
> > .max_register = 0x39,
> > /* Setting bits 7 and 6 enables multiple-byte read */
> > .read_flag_mask = BIT(7) | BIT(6),
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > [ADXL314] = {
> > .reg_bits = 8,
> > @@ -42,6 +46,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
> > .max_register = 0x39,
> > /* Setting bits 7 and 6 enables multiple-byte read */
> > .read_flag_mask = BIT(7) | BIT(6),
> > + .volatile_reg = adxl313_is_volatile_reg,
> > + .cache_type = REGCACHE_MAPLE,
> > },
> > };
> >
>
