On 07. 05. 25 3:41 odp., Andy Shevchenko wrote:
On Wed, May 7, 2025 at 3:45 PM Ivan Vecera <ivecera@xxxxxxxxxx> wrote:
Register DPLL sub-devices to expose the functionality provided
by ZL3073x chip family. Each sub-device represents one of
the available DPLL channels.
...
+static const struct zl3073x_pdata zl3073x_pdata[ZL3073X_MAX_CHANNELS] = {
+ { .channel = 0, },
+ { .channel = 1, },
+ { .channel = 2, },
+ { .channel = 3, },
+ { .channel = 4, },
+};
+static const struct mfd_cell zl3073x_devs[] = {
+ ZL3073X_CELL("zl3073x-dpll", 0),
+ ZL3073X_CELL("zl3073x-dpll", 1),
+ ZL3073X_CELL("zl3073x-dpll", 2),
+ ZL3073X_CELL("zl3073x-dpll", 3),
+ ZL3073X_CELL("zl3073x-dpll", 4),
+};
+#define ZL3073X_MAX_CHANNELS 5
Btw, wouldn't be better to keep the above lists synchronised like
1. Make ZL3073X_CELL() to use indexed variant
[idx] = ...
2. Define the channel numbers
and use them in both data structures.
...
WDYM?
OTOH, I'm not sure why we even need this. If this is going to be
sequential, can't we make a core to decide which cell will be given
which id?
Just a note that after introduction of PHC sub-driver the array will
look like:
static const struct mfd_cell zl3073x_devs[] = {
ZL3073X_CELL("zl3073x-dpll", 0), // DPLL sub-dev for chan 0
ZL3073X_CELL("zl3073x-phc", 0), // PHC sub-dev for chan 0
ZL3073X_CELL("zl3073x-dpll", 1), // ...
ZL3073X_CELL("zl3073x-phc", 1),
ZL3073X_CELL("zl3073x-dpll", 2),
ZL3073X_CELL("zl3073x-phc", 2),
ZL3073X_CELL("zl3073x-dpll", 3),
ZL3073X_CELL("zl3073x-phc", 3),
ZL3073X_CELL("zl3073x-dpll", 4),
ZL3073X_CELL("zl3073x-phc", 4), // PHC sub-dev for chan 4
};
Ivan
