Carve out a space for folks to explain existing tiering mechanisms and how CXL capacity interacts with it. Signed-off-by: Gregory Price <gourry@xxxxxxxxxx> --- .../driver-api/cxl/allocation/tiering.rst | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/driver-api/cxl/allocation/tiering.rst diff --git a/Documentation/driver-api/cxl/allocation/tiering.rst b/Documentation/driver-api/cxl/allocation/tiering.rst new file mode 100644 index 000000000000..623bb23088be --- /dev/null +++ b/Documentation/driver-api/cxl/allocation/tiering.rst @@ -0,0 +1,31 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============== +Memory Tiering +============== + +todo + +Memory Tiers +============ + +todo + + +Transparent Page Placement +========================== + +todo + +Data Access MONitor +=================== + +to be updated + +References +---------- + +- `Self-tuned Memory Tiering RFC prototype and its evaluation <https://lore.kernel.org/all/20250320053937.57734-1-sj@xxxxxxxxxx/>`_ +- `SK Hynix HMSDK Capacity Expansion <https://github.com/skhynix/hmsdk/wiki/Capacity-Expansion>`_ +- `kernel documentation <https://origin.kernel.org/doc/html/latest/mm/damon/>`_ +- `project website <https://damonitor.github.io/>`_ -- 2.49.0
