On 04/09, David Lechner wrote: > On 3/27/25 4:24 PM, Marcelo Schmitt wrote: > > FPGA HDL projects can include a PWM generator in addition to SPI-Engine. > > The PWM IP is used to trigger SPI-Engine offload modules that in turn set > > SPI-Engine to execute transfers to poll data from the ADC. That allows data > > to be read at the maximum sample rates. Also, it is possible to set a > > specific sample rate by setting the proper PWM duty cycle and related state > > parameters, thus allowing an adjustable ADC sample rate when a PWM (offload > > trigger) is used in combination with SPI-Engine. > > > > Add support for SPI offload. > > > > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@xxxxxxxxxx> > > --- > > I think I spotted a bug. With that fixed... > > Reviewed-by: David Lechner <dlechner@xxxxxxxxxxxx> > > > @@ -690,6 +942,15 @@ static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st, > > > > xfers[1].rx_buf = &st->scan.data; > > xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); > > Now this needs to be: > > xfer->len = chan->scan_type.realbits > 16 ? 4 : 2; > > Otherwise when there is SPI offload, this could read 2 words because > storagebits is always == 32. I've just tested both versions with ADAQ4003 and with AD7687. There's no practical difference between the suggestion and what already is in IIO testing. I don't mind sending a patch with the change, but don't think it fixes anything. Thanks, Marcelo
