On Tue, Feb 25, 2025 at 12:17 AM Anshuman Khandual
<anshuman.khandual@xxxxxxx> wrote:
>
>
>
> On 2/24/25 19:41, Mark Rutland wrote:
> > On Mon, Feb 03, 2025 at 10:38:28AM +0530, Anshuman Khandual wrote:
> >> FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1
> >> access from EL1 requires appropriate EL2 fine grained trap configuration
> >> via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2.
> >> Otherwise such register accesses will result in traps into EL2.
> >>
> >> Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine
> >> grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the
> >> bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into
> >> PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers.
> >>
> >> Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2
> >> based registers to be accessible in EL2.
> >>
> >> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
> >> Cc: Will Deacon <will@xxxxxxxxxx>
> >> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> >> Cc: Rob Herring <robh@xxxxxxxxxx>
> >> Cc: Jonathan Corbet <corbet@xxxxxxx>
> >> Cc: Marc Zyngier <maz@xxxxxxxxxx>
> >> Cc: Oliver Upton <oliver.upton@xxxxxxxxx>
> >> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> >> Cc: linux-doc@xxxxxxxxxxxxxxx
> >> Cc: linux-kernel@xxxxxxxxxxxxxxx
> >> Cc: kvmarm@xxxxxxxxxxxxxxx
> >> Tested-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> >> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
> >> ---
> >> Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++
> >> arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++
> >> 2 files changed, 43 insertions(+)
> >
> > Three things to note here:
> >
> > (1) I think this is missing some other necessary register configuration.
> >
> > From a quick scan, we also require MDCR_EL3.EnPM2 (bit [7]) to be
> > configured, which is not described in mainline nor here. If that
>
> Will update the Documentation/arch/arm64/booting.rst.
>
> > resets to 0, then EL{2,1,0} accesses to a number of registers such
> > as PMUACR_EL1 may trap to EL3>
> > AFAICT the boot-wrapper resets that bit to 0, so have we actually
> > tested all of this with the boot-wrapper? Does TF-A set this bit?
>
> Right, boot wrapper resets the bit to 0. We will need the following changes
> to set that up when PMUv3p9 is available. MDCR_EL3.EnPM2 also needs to be
> set when FEAT_SPMU, FEAT_EBEP, FEAT_PMUv3_SS or FEAT_SPMU2 are implemented.
> Should those features be checked here as well ?
