On Thu, Jul 10, 2025 at 02:33:39PM +0100, Suman Kumar Chakraborty wrote: > This patch set introduces and extends the rate limiting (RL) infrastructure > in the Intel QAT (QuickAssist Technology) driver, with a focus on enabling > RL support for QAT GEN6 devices and enhancing support for decompression > service. > > The series begins by enforcing service validation in the RL sysfs API to > prevent misconfiguration. It then adds decompression (DECOMP) service, > including its enumeration and visibility via sysfs. Subsequently, service > enums are refactored and consolidated to remove duplication and clearly > differentiate between base and extended services. > > Further patches improve modularity by relocating is_service_enabled() into > the appropriate C file, introduce a flexible mechanism using > adf_rl_get_num_svc_aes() and get_svc_slice_cnt() APIs, and implement these > for both GEN4 and GEN6 platforms. Additionally, the compression slice count > (cpr_cnt) is now cached for use within the RL infrastructure. > > Finally, the series enables full RL support for GEN6 by initializing the > rl_data and implementing platform-specific logic to query acceleration > engines and slice counts for QAT GEN6 hardware. > > Summary of Changes: > > Patch #1 Validates service in RL sysfs API. > Patch #2 Adds decompression (DECOMP) service to RL to enable SLA support for > DECOMP where supported (e.g., GEN6). > Patch #3 Consolidated the service enums. > Patch #4 Relocates the is_service_enabled() function to improve modularity and > aligns code structure. > Patch #5 Adds adf_rl_get_num_svc_aes() to enable querying number of engines per > service. > Patch #6 Adds get_svc_slice_cnt() to device data to generalizes AE count lookup. > Patch #7 Adds compression slice count tracking. > Patch #8 Enables RL for GEN6. > > Suman Kumar Chakraborty (8): > crypto: qat - validate service in rate limiting sysfs api > crypto: qat - add decompression service for rate limiting > crypto: qat - consolidate service enums > crypto: qat - relocate service related functions > crypto: qat - add adf_rl_get_num_svc_aes() in rate limiting > crypto: qat - add get_svc_slice_cnt() in device data structure > crypto: qat - add compression slice count for rate limiting > crypto: qat - enable rate limiting feature for GEN6 devices > > Documentation/ABI/testing/sysfs-driver-qat_rl | 14 +-- > .../intel/qat/qat_420xx/adf_420xx_hw_data.c | 9 +- > .../intel/qat/qat_4xxx/adf_4xxx_hw_data.c | 9 +- > .../intel/qat/qat_6xxx/adf_6xxx_hw_data.c | 77 ++++++++++++++++- > .../intel/qat/qat_6xxx/adf_6xxx_hw_data.h | 20 +++++ > .../intel/qat/qat_common/adf_accel_devices.h | 2 + > .../intel/qat/qat_common/adf_cfg_services.c | 40 ++++++++- > .../intel/qat/qat_common/adf_cfg_services.h | 12 ++- > .../intel/qat/qat_common/adf_gen4_hw_data.c | 42 ++++++++- > .../intel/qat/qat_common/adf_gen4_hw_data.h | 3 + > drivers/crypto/intel/qat/qat_common/adf_rl.c | 86 ++++++------------- > drivers/crypto/intel/qat/qat_common/adf_rl.h | 11 +-- > .../intel/qat/qat_common/adf_rl_admin.c | 1 + > .../intel/qat/qat_common/adf_sysfs_rl.c | 21 +++-- > 14 files changed, 251 insertions(+), 96 deletions(-) > > > base-commit: db689623436f9f8b87c434285a4bdbf54b0f86d2 > -- > 2.40.1 All applied. Thanks. -- Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
