From: Florian Fainelli <f.fainelli@xxxxxxxxx> On Mon, 12 May 2025 14:05:50 +0200, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > All the BCMBCA SoCs share a set of peripherals at 0xff800000, > albeit at slightly varying memory locations on the bus and > with varying IRQ assignments. > > Add the first and second watchdog, GPIO, RNG, LED, DMA and > second PL011 UART blocks for the BCM6855 based on the vendor > files 6855_map_part.h and 6855_intr.h from the > "bcmopen-consumer" code drop. > > This SoC has up to 256 possible GPIOs due to having 8 > registers with 32 GPIOs in each available. > > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian
