Hi Linus, > -----Original Message----- > From: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx> > Sent: Saturday, April 26, 2025 1:49 AM > To: Linus Walleij <linus.walleij@xxxxxxxxxx>; Rob Herring > <robh@xxxxxxxxxx>; > Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley > <conor+dt@xxxxxxxxxx>; William Zhang <william.zhang@xxxxxxxxxxxx>; > Anand Gore <anand.gore@xxxxxxxxxxxx>; Kursad Oney > <kursad.oney@xxxxxxxxxxxx>; Florian Fainelli > <florian.fainelli@xxxxxxxxxxxx>; Rafał Miłecki <rafal@xxxxxxxxxx>; > Broadcom > internal kernel review list <bcm-kernel-feedback-list@xxxxxxxxxxxx>; > Olivia > Mackall <olivia@xxxxxxxxxxx>; Ray Jui <rjui@xxxxxxxxxxxx>; Scott Branden > <sbranden@xxxxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; > linux- > crypto@xxxxxxxxxxxxxxx; Krzysztof Kozlowski > <krzysztof.kozlowski@xxxxxxxxxx> > Subject: Re: [PATCH v2 00/12] ARM: bcm: Add some BCMBCA peripherals > > > > On 4/6/2025 5:32 PM, Linus Walleij wrote: > > This adds a bunch peripherals to the Broadcom BRCMBCA > > SoC:s that I happened to find documentation for in some > > vendor header files. > > > > It started when I added a bunch of peripherals for the > > BCM6846, and this included really helpful peripherals > > such as the PL081 DMA, for which I think the most common > > usecase is to be used as a memcpy engine to offload > > transfer of blocks from NAND flash to/from the NAND > > flash controller (at least this is how the STMicro > > FSMC controller was using it). > > > > So I took a sweep and added all the stuff that has > > bindings to: > > > > ARM: > > - BCM6846 > > - BCM6855 > > - BCM6878 > > - BCM63138 > > - BCM63148 > > - BCM63178 > > > > ARM64: > > - BCM4908 > > - BCM6856 > > - BCM6858 > > - BCM63158 > > > > There are several "holes" in this SoC list, I simply > > just fixed those that I happened to run into documentation > > for. > > > > Unfortunately while very similar, some IP blocks vary > > slightly in version, the GPIO block is differently > > integrated on different systems, and the interrupt assignments > > are completely different, so it's safest to add these to each > > DTSI individually. > > > > I add the interrupt binding for the RNG block in the > > process as this exists even if Linux isn't using the > > IRQ, and I put the RNG and DMA engines as default-enabled > > because they are not routed to the outside and should > > "just work" so why not. > > > > I did a rogue patch adding some stuff to BCM6756 based > > on guessed but eventually dropped it. If someone has > > docs for this SoC I can add it. > > > > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > > Linus can you resubmit a v3 addressing William's feedback? I will drop > your series for now. Thanks! > -- > Florian I wonder if you get a chance to review my feedbacks on this series? Let me know if you have any questions. Thanks, William
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