From: Pavitrakumar Managutte <pavitrakumarm@xxxxxxxxxxxxxxx> Add DT bindings related to the SPAcc driver for Documentation. DWC Synopsys Security Protocol Accelerator(SPAcc) Hardware Crypto Engine is a crypto IP designed by Synopsys. Co-developed-by: Bhoomika Kadabi <bhoomikak@xxxxxxxxxxxxxxx> Signed-off-by: Bhoomika Kadabi <bhoomikak@xxxxxxxxxxxxxxx> Signed-off-by: Pavitrakumar Managutte <pavitrakumarm@xxxxxxxxxxxxxxx> Acked-by: Ruud Derwig <Ruud.Derwig@xxxxxxxxxxxx> --- .../bindings/crypto/snps,dwc-spacc.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/snps,dwc-spacc.yaml diff --git a/Documentation/devicetree/bindings/crypto/snps,dwc-spacc.yaml b/Documentation/devicetree/bindings/crypto/snps,dwc-spacc.yaml new file mode 100644 index 000000000000..190c0a3f6d6a --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/snps,dwc-spacc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/snps,dwc-spacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare Security Protocol Accelerator(SPAcc) Crypto Engine + +maintainers: + - Ruud Derwig <Ruud.Derwig@xxxxxxxxxxxx> + +description: | + This binding describes the Synopsys DWC Security Protocol Accelerator (SPAcc), + which is a hardware IP designed to accelerate cryptographic operations, such + as encryption, decryption, and hashing. + + The SPAcc supports virtualization where a single physical SPAcc can be + accessed as multiple virtual SPAcc instances, each with its own register set. + These virtual instances can be assigned different priorities for hardware + arbitration of crypto operation processing. + + The SPAcc IP has been instantiated in programmable logic (PL) of Xilinx + ZynqMP(zcu-104), connected as a memory-mapped peripheral on the system bus, + and accessed through a standard interrupt routed to the GIC. This binding + describes a standalone instantiation of SPAcc IP, without SoC-specific + customization. + +properties: + compatible: + items: + - const: snps,dwc-spacc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + snps,vspacc-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Virtual SPAcc instance identifier. + The SPAcc hardware supports multiple virtual instances (determined by + ELP_SPACC_CONFIG_VSPACC_CNT parameter), and this ID is used to identify + which virtual instance this node represents. + minimum: 0 + maximum: 7 + + snps,spacc-internal-counter: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Hardware counter that generates an interrupt based on a count value. + This counter starts ticking when there is a completed job sitting on + the status fifo to be serviced. This makes sure that no jobs are + starved of processing. + minimum: 0x19000 + maximum: 0xFFFFF + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + crypto@40000000 { + compatible = "snps,dwc-spacc"; + reg = <0x40000000 0x3FFFF>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock>; + snps,spacc-internal-counter = <0x20000>; + snps,vspacc-id = <0>; + }; -- 2.25.1
