From: Florian Fainelli <f.fainelli@xxxxxxxxx> On Sun, 06 Apr 2025 17:32:52 +0200, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > All the BCMBCA SoCs share a set of peripherals at 0xff800000, > albeit at slightly varying memory locations on the bus and > with varying IRQ assignments. On BCM63158 the PERF window was > too big so adjust it down to its real size (0x3000). > > Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA > blocks for the BCM63158 based on the vendor files 63158_map_part.h > and 63158_intr.h from the "bcmopen-consumer" code drop. > > The DTSI file has clearly been authored for the B0 revision of > the SoC: there is an earlier A0 version, but this has > the UARTs in the legacy PERF memory space, while the B0 > has opened a new peripheral window at 0xff812000 for the > three UARTs. It also has a designated AHB peripheral area > at 0xff810000 where the DMA resides, so we create new windows > for these two peripheral group reflecting the internal > structure of the B0 SoC. > > This SoC has up to 256 possible GPIOs due to having 8 > registers with 32 GPIOs in each available. > > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks! -- Florian
