> From the UFSHCI 4.0 specification, about the MCQ mode: > "Command Submission > 1. Host SW writes an Entry to SQ > 2. Host SW updates SQ doorbell tail pointer > > Command Processing > 3. After fetching the Entry, Host Controller updates SQ doorbell head > pointer > 4. Host controller sends COMMAND UPIU to UFS device" > > In other words, in MCQ mode, UFS controllers are required to forward > commands to the UFS device in the order these commands have been > received from the host. > > This patch improves performance as follows on a test setup with UFSHCI > 4.0 controller: > - With the mq-deadline scheduler: 2.0x more IOPS for small writes. > - When not using an I/O scheduler compared to using mq-deadline with > zone locking: 2.3x more IOPS for small writes. > > Cc: Bao D. Nguyen <quic_nguyenb@xxxxxxxxxxx> > Cc: Can Guo <quic_cang@xxxxxxxxxxx> > Cc: Martin K. Petersen <martin.petersen@xxxxxxxxxx> > Cc: Avri Altman <avri.altman@xxxxxxx> > Signed-off-by: Bart Van Assche <bvanassche@xxxxxxx> Reviewed-by: Avri Altman <avri.altman@xxxxxxxxxxx> > --- > drivers/ufs/core/ufshcd.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c > index 4410e7d93b7d..340db59b7675 100644 > --- a/drivers/ufs/core/ufshcd.c > +++ b/drivers/ufs/core/ufshcd.c > @@ -5281,6 +5281,12 @@ static int ufshcd_sdev_configure(struct > scsi_device *sdev, > struct ufs_hba *hba = shost_priv(sdev->host); > struct request_queue *q = sdev->request_queue; > > + /* > + * The write order is preserved per MCQ. Without MCQ, auto-hibernation > + * may cause write reordering that results in unaligned write errors. > + */ > + lim->driver_preserves_write_order = hba->mcq_enabled; > + > lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; > > /*
