From: Yijie Yang <quic_yijiyang@xxxxxxxxxxx>
Add an ethernet controller node for QCS615 SoC to enable ethernet
functionality.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Signed-off-by: Yijie Yang <quic_yijiyang@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm6150.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 591fcb740259..8ec97532911c 100644
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -491,6 +491,39 @@ soc: soc@0 {
dma-ranges = <0 0 0 0 0x10 0>;
#address-cells = <2>;
#size-cells = <2>;
+ ethernet: ethernet@20000 {
+ compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos";
+ reg = <0x0 0x00020000 0x0 0x10000>,
+ <0x0 0x00036000 0x0 0x100>;
+ reg-names = "stmmaceth",
+ "rgmii";
+
+ clocks = <&gcc GCC_EMAC_AXI_CLK>,
+ <&gcc GCC_EMAC_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC_PTP_CLK>,
+ <&gcc GCC_EMAC_RGMII_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "rgmii";
+
+ interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_lpi";
+
+ power-domains = <&gcc EMAC_GDSC>;
+ resets = <&gcc GCC_EMAC_BCR>;
+
+ iommus = <&apps_smmu 0x1c0 0x0>;
+
+ snps,tso;
+ snps,pbl = <32>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <20480>;
+
+ status = "disabled";
+ };
gcc: clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
--
2.34.1
