Add Operation State Manager (OSM) L3 scaling support on QCS615 SoC. This series has dependency on [1]. [1] https://lore.kernel.org/all/20250814-qcs615-mm-cpu-dt-v6-v6-0-a06f69928ab5@xxxxxxxxxxxxxxxx/ Changes since v2: - Updated SoB sequence [Dmitry]. - Addressed review comments related to reg field in device node [Dmitry]. - Updated the commit text as per review comment [Krzysztof] - Link to v2: https://lore.kernel.org/all/20250804061536.110-1-raviteja.laggyshetty@xxxxxxxxxxxxxxxx/ Changes since v1: - Updated dependency on cpufreq patch [Imran]. - Updated SoB sequence [Dmitry]. - Link to v1: https://lore.kernel.org/all/20250804050542.100806-1-raviteja.laggyshetty@xxxxxxxxxxxxxxxx/ Raviteja Laggyshetty (2): dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3 .../bindings/interconnect/qcom,osm-l3.yaml | 5 + arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 ++++++++++++++++++ 2 files changed, 153 insertions(+) -- 2.43.0 --- Raviteja Laggyshetty (2): dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3 .../bindings/interconnect/qcom,osm-l3.yaml | 5 + arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 +++++++++++++++++++++ 2 files changed, 153 insertions(+) --- base-commit: 43c3c17f0c805882d1b48818b1085747a68c80ec change-id: 20250819-talos-l3-icc-0760779a1cc7 prerequisite-change-id: 20250813-qcs615-mm-cpu-dt-v6-cd303ce46b83:v6 prerequisite-patch-id: 4b94c7a005b2dec7b172b82451c1d7c0d155b4bc prerequisite-patch-id: 7952264a4038f09c49fe4a5f75c7bfdf26d2d04b Best regards, -- Raviteja Laggyshetty <raviteja.laggyshetty@xxxxxxxxxxxxxxxx>
