On Fri, Aug 22, 2025 at 11:39:16AM +0200, Neil Armstrong wrote:
> Allow up to 4 lanes for the DisplayPort link from the PHYs to the
> controllers now the mode-switch events can reach the QMP Combo PHYs.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index 9dfb248f9ab52b354453cf42c09d93bbee99214f..6c2c9514a7396a8b75ebe24585b47571c74ff568 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -1003,7 +1003,7 @@ &mdss_dp0 {
> };
>
> &mdss_dp0_out {
> - data-lanes = <0 1>;
> + data-lanes = <0 1 2 3>;
On most of these platforms the data lanes between DP and combo PHY are
hardwired. I'd suggest moving the data-lanes to the SoC dtsi (at least
for USB-C-wrapped DP controllers).
> };
>
> &pcie0 {
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
