On Mon, Aug 25, 2025 at 10:16:04PM +0800, Yongxing Mou wrote: > From: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx> > > Add support to program the MST enable bit in the mainlink control > register when an MST session is active or being disabled. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx> > Signed-off-by: Yongxing Mou <yongxing.mou@xxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ > drivers/gpu/drm/msm/dp/dp_reg.h | 1 + > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h > index de3d0b8b52c269fd7575edf3f4096a4284ad0b8d..fda847b33f8d0d6ec4d2589586b5a3d6c9b1ccf3 100644 > --- a/drivers/gpu/drm/msm/dp/dp_reg.h > +++ b/drivers/gpu/drm/msm/dp/dp_reg.h > @@ -128,6 +128,7 @@ > #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) > #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) > #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) > +#define DP_MAINLINK_CTRL_MST_EN (0x04000100) Why are there two bits? > > #define REG_DP_STATE_CTRL (0x00000004) > #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) > > -- > 2.34.1 > -- With best wishes Dmitry
