From: Jessica Zhang <jessica.zhang@xxxxxxxxxxxxxxxx>
Update Qualcomm DT files in order to declare extra stream pixel clocks
and extra register resources used on these platforms to support
DisplayPort MST.
Signed-off-by: Jessica Zhang <jessica.zhang@xxxxxxxxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 46 +++++++++++++++++-----
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 23 +++++++----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++--
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
13 files changed, 185 insertions(+), 74 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 64f5378c6a4770cee2c7d76cde1098d7df17a24a..a1e033089860504844727fd9cd887f0808de1607 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4694,7 +4694,11 @@ mdss0_dp0: displayport-controller@af54000 {
<0x0 0x0af54200 0x0 0x0c0>,
<0x0 0x0af55000 0x0 0x770>,
<0x0 0x0af56000 0x0 0x09c>,
- <0x0 0x0af57000 0x0 0x09c>;
+ <0x0 0x0af57000 0x0 0x09c>,
+ <0x0 0x0af58000 0x0 0x09c>,
+ <0x0 0x0af59000 0x0 0x09c>,
+ <0x0 0x0af5a000 0x0 0x23c>,
+ <0x0 0x0af5b000 0x0 0x23c>;
interrupt-parent = <&mdss0>;
interrupts = <12>;
@@ -4703,15 +4707,28 @@ mdss0_dp0: displayport-controller@af54000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp0_phy 0>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
@@ -4773,7 +4790,11 @@ mdss0_dp1: displayport-controller@af5c000 {
<0x0 0x0af5c200 0x0 0x0c0>,
<0x0 0x0af5d000 0x0 0x770>,
<0x0 0x0af5e000 0x0 0x09c>,
- <0x0 0x0af5f000 0x0 0x09c>;
+ <0x0 0x0af5f000 0x0 0x09c>,
+ <0x0 0x0af60000 0x0 0x09c>,
+ <0x0 0x0af61000 0x0 0x09c>,
+ <0x0 0x0af62000 0x0 0x23c>,
+ <0x0 0x0af63000 0x0 0x23c>;
interrupt-parent = <&mdss0>;
interrupts = <13>;
@@ -4782,15 +4803,20 @@ mdss0_dp1: displayport-controller@af5c000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp1_phy 0>,
+ <&mdss0_dp1_phy 1>,
+ <&mdss0_dp1_phy 1>;
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index 38f7869616ff01ece3799ced15c39375d629e364..62bd535d7f14bed10fae329b20ac97cb63f3761b 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 0dd6a5c91d109c78333f6b90104fa51fcf3bd64c..375e890f02c7d1cb06845293f17deb6ec45f9c5a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5047,7 +5047,8 @@ mdss_edp: edp@aea0000 {
reg = <0 0x0aea0000 0 0x200>,
<0 0x0aea0200 0 0x200>,
<0 0x0aea0400 0 0xc00>,
- <0 0x0aea1000 0 0x400>;
+ <0 0x0aea1000 0 0x400>,
+ <0 0x0aea1400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 70c87c79e1325f4ab4c81f34e99c0b52be4b3810..e6a7248040095077d6f98d632f4e8a1868432445 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3241,16 +3241,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
@@ -3319,16 +3323,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
@@ -3389,7 +3397,8 @@ mdss_edp: displayport-controller@ae9a000 {
reg = <0 0xae9a000 0 0x200>,
<0 0xae9a200 0 0x200>,
<0 0xae9a400 0 0x600>,
- <0 0xae9aa00 0 0x400>;
+ <0 0xae9aa00 0 0x400>,
+ <0 0xae9b000 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 421693208af0d5baeaa14ba2bbf29cbbc677e732..ad04868763d00221ed9939c76132977b83762cd7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 {
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 {
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss0>;
interrupts = <14>;
phys = <&mdss0_dp2_phy>;
@@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp2_phy 0>,
+ <&mdss0_dp2_phy 1>,
+ <&mdss0_dp2_phy 1>;
operating-points-v2 = <&mdss0_dp2_opp_table>;
#sound-dai-cells = <0>;
@@ -5675,10 +5688,12 @@ mdss1_dp0: displayport-controller@22090000 {
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <12>;
phys = <&mdss1_dp0_phy>;
@@ -5686,8 +5701,11 @@ mdss1_dp0: displayport-controller@22090000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
operating-points-v2 = <&mdss1_dp0_opp_table>;
#sound-dai-cells = <0>;
@@ -5750,10 +5768,12 @@ mdss1_dp1: displayport-controller@22098000 {
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <13>;
phys = <&mdss1_dp1_phy>;
@@ -5761,8 +5781,11 @@ mdss1_dp1: displayport-controller@22098000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
operating-points-v2 = <&mdss1_dp1_opp_table>;
#sound-dai-cells = <0>;
@@ -5825,10 +5848,12 @@ mdss1_dp2: displayport-controller@2209a000 {
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <14>;
phys = <&mdss1_dp2_phy>;
@@ -5836,8 +5861,11 @@ mdss1_dp2: displayport-controller@2209a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp2_phy 0>,
+ <&mdss1_dp2_phy 1>,
+ <&mdss1_dp2_phy 1>;
operating-points-v2 = <&mdss1_dp2_opp_table>;
#sound-dai-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 828b55cb6baf10458feae8f53c04663ef958601e..816987906ca51b8c7eb834d8b850839941eadb6b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
- clock-names = "core_iface", "core_aux", "ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 4b347ee3244100a4db515515b73575383c5a0cb7..e0beb5373cdc8ff92f165d7a971f8f7dce31bca8 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 244339cfbed5c32708c282de18f5655535e2ff45..272b41214ab31edd2c0c695cf294f0959167585a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 9a4207ead6156333b8b6030fb0fbc1d215948041..136f40a3b9767133d6a4fe52753530bccced3391 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 2baef6869ed7c17efb239e86013c15ef6ef5f48f..1b482dc5f574acd5ea938c9953a35164e51c6cb3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 38d139d1dd4a994287c03d064ca01d59a11ac771..2d085680afd1bed2bd2477c21ae4b798efe6a066 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3755,16 +3755,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index d6794901f06b50e8629afd081cb7d229ea342f84..887b2ea055e8d969ba9ad07e738dcb6feccc0e61 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5657,16 +5657,20 @@ mdss_dp0: displayport-controller@af54000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&dp_opp_table>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index f293b13ecc0ce426661187ac793f147d12434fcb..7c5f6c101ac10ce6fbc5eead177246ce77c668bf 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5338,16 +5338,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
@@ -5421,16 +5425,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp1_opp_table>;
@@ -5504,16 +5512,20 @@ mdss_dp2: displayport-controller@ae9a000 {
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp2_opp_table>;
--
2.47.2
