On Wed, Sep 03, 2025 at 05:48:40PM +0200, Konrad Dybcio wrote:
> On 9/3/25 1:47 PM, Wasim Nazir wrote:
> > From: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
> >
> > Introduce the SDHC v5 controller node for the Lemans platform.
> > This controller supports either eMMC or SD-card, but only one
> > can be active at a time. SD-card is the preferred configuration
> > on Lemans targets, so describe this controller.
> >
> > Define the SDC interface pins including clk, cmd, and data lines
> > to enable proper communication with the SDHC controller.
> >
> > Signed-off-by: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
> > Co-developed-by: Wasim Nazir <wasim.nazir@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Wasim Nazir <wasim.nazir@xxxxxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/lemans.dtsi | 91 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 91 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > index 99a566b42ef2..9e4709dce32b 100644
> > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > @@ -3834,6 +3834,57 @@ apss_tpdm2_out: endpoint {
> > };
> > };
> >
> > + sdhc: mmc@87c4000 {
> > + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
> > + reg = <0x0 0x087c4000 0x0 0x1000>;
> > +
> > + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq", "pwr_irq";
>
> 1 entry per line in xx-names too, please> +
Ack.
> > + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> > + <&gcc GCC_SDCC1_APPS_CLK>;
> > + clock-names = "iface", "core";
> > +
> > + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
> > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
>
> QCOM_ICC_TAG_ALWAYS for the first path, both endpoints
> QCOM_ICC_TAG_ACTIVE_ONLY for the second one
Ack.
>
> [...]
>
> > +
> > + data-pins {
> > + pins = "sdc1_data";
> > + bias-pull-up;
>
> Please put bias properties below drive-strength for consistency
>
Ack.
> Konrad
--
Regards,
Wasim
