On Thu, Sep 04, 2025 at 02:52:23PM +0800, Ziyue Zhang wrote:
> Add lane equalization setting for 8.0 GT/s and 32.0 GT/s to enhance link
> stability and avoid AER Correctable Errors reported on some platforms
> (eg. SA8775P).
>
> 8.0 GT/s, 16.0 GT/s and 32.0 GT/s require the same equalization setting.
> This setting is programmed into a group of shadow registers, which can be
> switched to configure equalization for different speeds by writing 00b,
> 01b and 10b to `RATE_SHADOW_SEL`.
>
> Hence program equalization registers in a loop using link speed as index,
> so that equalization setting can be programmed for 8.0 GT/s, 16.0 GT/s
> and 32.0 GT/s.
>
> Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
>
Drop this blank line.
> Co-developed-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@xxxxxxxxxxxxxxxx>
> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
> + for (speed = PCIE_SPEED_8_0GT; speed <= pcie_link_speed[pci->max_link_speed]; ++speed) {
Use "speed++" when there's no need for preincrement to follow typical
drivers/pci/ usage.
No need to repost for these.
