On Mon, Sep 08, 2025 at 04:11:22PM +0530, Sarthak Garg wrote: > Due to an implementation detail in this SoC, additional passive > electrical components are required to achieve the maximum rated speed > of the SD controller when paired with a High-Speed SD Card. Without > them, the clock frequency must be limited to 37.5 MHz for link stability. > > Because the reference design does not contain these components, most > (derivative) boards do not have them either. To accommodate for that, > apply the frequency limit by default and delegate lifting it to the > odd boards that do contain the necessary onboard hardware. > > Signed-off-by: Sarthak Garg <quic_sartgarg@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
