On Thu, Aug 07, 2025 at 04:07:24PM +0100, Bryan O'Donoghue wrote: > On 07/08/2025 15:17, Neil Armstrong wrote: > > > > > > https://lore.kernel.org/linux-media/20250711-b4-linux-next-25-03-13- > > > dtsi-x1e80100-camss-v7-0-0bc5da82f526@xxxxxxxxxx > > > > > > V2 of the CSIPHY above will incorporate feedback from Neil and > > > yourself on adding endpoint@ to the PHY however I think we need to > > > have a conversation about standards compliance at attaching two > > > sensors to one CSIPHY without VCs or TDM. > > > > The PHY is able to setup 2 lanes as clock and connect 2 sensors over the > > 5 lanes available, like for example: > > - lane0: cam0 data0 > > - lane1: cam0 data1 > > - lane2: cam1 data0 > > - lane3: cam1 clk > > - lane4: cam0 clk > > > > Any lane mapping is compliant. There some Meta slides about that at: > > https://www.edge-ai-vision.com/wp-content/uploads/2024/09/T2R10_Kumaran- > > Ayyalluseshagiri-Viswanathan_Meta_2024.pdf slide 13 > > Hmm so that would require splitting the CSIPHY between two CSI decoders > which I'm not sure would work on our hardware, perhaps yes, perhaps no, or > routing both sensors into the one CSI decoder and then separating the > data-streams either in the driver or in user-space. The RB5 board provides exactly this setup on the CSI0. It can be switched between 4 lanes going to CSI0A and 2 (data) lanes going to the CSI0A and 1 (data) lane going to the CSI0B connector. > For such an esoteric setup I think my initial suggestion would be to push it > into user-space, even assuming you have gotten the PHY to co-operate with > having two simultaneous clock lanes per the above link. > > Looking at the PHY regs, I guess you can set the bits but obviously the > analogue component of the PHY can only really operate from the one clock > lane.... > > Interesting. > > --- > bod > > -- With best wishes Dmitry
