On 8/6/25 1:14 PM, Manivannan Sadhasivam wrote: > On Wed, Aug 06, 2025 at 12:04:09PM GMT, Palash Kambar wrote: >> Disable of AES core in Shared ICE is not supported during power >> collapse for UFS Host Controller V5.0. >> >> Hence follow below steps to reset the ICE upon exiting power collapse >> and align with Hw programming guide. >> >> a. Write 0x18 to UFS_MEM_ICE_CFG >> b. Write 0x0 to UFS_MEM_ICE_CFG >> >> Signed-off-by: Palash Kambar <quic_pkambar@xxxxxxxxxxx> >> --- [...] > >> + ufshcd_readl(hba, UFS_MEM_ICE); >> + ufshcd_writel(hba, 0x0, UFS_MEM_ICE); >> + ufshcd_readl(hba, UFS_MEM_ICE); > > Why do you need readl()? Writes to device memory won't get reordered. I'm not sure if we need a delay between them, otherwise they'll happen within a couple cycles of each other which may not be enough since this is a synchronous reset and the clock period is 20-50ns when running at XO (19.2 / 38.4 MHz) rate Konrad
