On Mon, Aug 04, 2025 at 02:34:56PM +0200, Konrad Dybcio wrote: > On 8/4/25 6:39 AM, Yongxing Mou wrote: > > > > > > On 2025/7/30 18:25, Konrad Dybcio wrote: > >> On 7/30/25 11:49 AM, Yongxing Mou wrote: > >>> Add devicetree changes to enable MDSS display-subsystem, > >>> display-controller(DPU), DisplayPort controller and eDP PHY for > >>> Qualcomm QCS8300 platform. > >>> > >>> Signed-off-by: Yongxing Mou <quic_yongmou@xxxxxxxxxxx> > >>> --- > >> > >> [...] > >> > >>> + > >>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; > >>> + assigned-clock-rates = <19200000>; > >> > >> is this necessary? > >> > > Emm, i try to remove assigned-clocks and assigned-clock-rates here, device can still work.. here we just want to keep consistent with sa8775p. > > Dmitry, do you remember whether this is some relic of the past that > was required at one point? I think it was necessary for old platforms (MSM8916, MSM8939, MSM8953, APQ8084, MSM8974, MSM8992/94, MSM8996, MSM8998, SDM630/660), which can source vsync_clk_src either from the XO or from the GPLL / MMPLL. > > The driver lists 19.2 as the only possible frequency for the source > of this branch -- With best wishes Dmitry
