On 8/4/25 1:20 PM, Varadarajan Narayanan wrote:
> From: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
>
> CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
> Add support for the APSS PLL, RCG and clock enable for ipq5424.
> The PLL, RCG register space are clubbed. Hence adding new APSS driver
> for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
> and needs to be scaled along with the CPU and is modeled as an ICC clock.
>
> Co-developed-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
> Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
> [ Removed clock notifier, moved L3 pll to icc-clk, used existing
> alpha pll structure ]
> Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
> ---
[...]
> +static struct clk_alpha_pll ipq5424_apss_pll = {
> + .offset = 0x0,
> + .config = &apss_pll_config,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .enable_reg = 0x0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "apss_pll",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_XO,
> + },
> + .parent_names = (const char *[]){ "xo-board-clk"},
Parent_data and parent_names are mutually exclusive
[...]
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> + },
> +};
> +
> +static const struct clk_parent_data parents_apss_silver_clk_src[] = {
> + { .index = DT_XO },
> + { .index = DT_CLK_REF },
> + { .hw = &ipq5424_apss_pll.clkr.hw },
> +};
You use indices here /\
[...]
But not here \/
> +static struct clk_alpha_pll ipq5424_l3_pll = {
> + .offset = 0x10000,
> + .config = &l3_pll_config,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .enable_reg = 0x0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "l3_pll",
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xo-board-clk",
> + },
> + .parent_names = (const char *[]){ "xo-board-clk"},
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> + },
> +};
> +
> +static const struct clk_parent_data parents_l3_clk_src[] = {
> + { .fw_name = "xo-board-clk" },
> + { .fw_name = "clk_ref" },
> + { .hw = &ipq5424_l3_pll.clkr.hw },
> +};
[...]
> + .hw.init = &(struct clk_init_data){
> + .name = "l3_clk",
> + .parent_hws = (const struct clk_hw *[]){
"clk_hw *[]) {"
Konrad
