On 25-08-01 10:02:15, Taniya Das wrote:
>
>
> On 7/30/2025 4:55 PM, Abel Vesa wrote:
> > On 25-07-29 11:12:37, Taniya Das wrote:
> >> Add a clock driver for the TCSR clock controller found on Glymur, which
> >> provides refclks for PCIE, USB, and UFS.
> >>
> >> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> >> ---
> >> drivers/clk/qcom/Kconfig | 8 ++
> >> drivers/clk/qcom/Makefile | 1 +
> >> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++
> >> 3 files changed, 266 insertions(+)
> >>
> >
> > [...]
> >
> >> +
> >> +static struct clk_branch tcsr_edp_clkref_en = {
> >> + .halt_reg = 0x1c,
> >> + .halt_check = BRANCH_HALT_DELAY,
> >> + .clkr = {
> >> + .enable_reg = 0x1c,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(const struct clk_init_data) {
> >> + .name = "tcsr_edp_clkref_en",
> >> + .ops = &clk_branch2_ops,
> >
> > As discussed off-list, these clocks need to have the bi_tcxo as parent.
> >
> > Otherwise, as far as the CCF is concerned these clocks will have rate 0,
> > which is obviously not the case.
> >
> > Bringing this here since there is a disconnect between X Elite and
> > Glymur w.r.t this now.
>
>
> The ref clocks are not required to be have a parent of bi_tcxo as these
> ideally can be left enabled(as a subsystem requirement) even if HLOS
> (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from
> HLOS/APSS will not allow APSS to collapse.
Is there a scenario where the APSS is collapsed and still the ref clock
needs to stay enabled ? Sorry, this doesn't make sense to me.
>
> If any consumers needs the clock rate, the driver should take the
> BI_TCXO handle.
This kind of breaks the CCF design. If the ref clock is a gate of the
bi_tcxo HW-wise, then not marking it so in CCF is wrong. Passing the
bi_tcxo to the PHYs separately because of this, makes the assumption that
the PHY drivers should know not to disable the bi_tcxo themselves
either.
>
>
> --
> Thanks,
> Taniya Das
>
