On 22/07/2025 09:22, Xiangxu Yin wrote: > Add support for specifying two TCSR register addresses in the > qcom,tcsr-reg property to enable DP-only mode switching. This change > maintains backward compatibility with the original single-register > format. > > Also update #clock-cells and #phy-cells to <1> to support clock and PHY > provider interfaces, respectively. This is required for platforms that > consume the PHY clock and select PHY mode dynamically. > > Signed-off-by: Xiangxu Yin <xiangxu.yin@xxxxxxxxxxxxxxxx> > --- > .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 28 +++++++++++++++++----- > 1 file changed, 22 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00d97dc2ba742d6 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > @@ -44,13 +44,21 @@ properties: > vdda-pll-supply: true > > "#clock-cells": > - const: 0 > + oneOf: > + - description: Set to 0 for legacy platforms without clock provider > + const: 0 > + - description: Set to 1 to expose PHY pipe clock. > + const: 1 > > clock-output-names: > maxItems: 1 > > "#phy-cells": > - const: 0 > + oneOf: > + - description: Set to 0 for legacy platforms > + const: 0 > + - description: Set to 1 to supports mode selection (e.g. USB/DP) > + const: 1 I don't understand why EXISTING platforms now get more clocks. What did you change in the hardware? This you must explain in the commit msg. Best regards, Krzysztof
