qcs9100 SOC is IOT variant of sa8775p SOC and it supports safety
monitoring feature of Safety Island(SAIL) subsystem.
qcs9100-som.dtsi specifies qcs9100 based SOM having SOC, PMICs
& Memory-map updates (not added currently as part of code refactoring).
qcs9100-ride-r3 board is based on QCS9100M SOM.
qcs9100-ride-r3 also supports 2.5G ethernet phy i.e aqr115c.
Signed-off-by: Wasim Nazir <quic_wasimn@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 10 +++++++---
arch/arm64/boot/dts/qcom/qcs9100-som.dtsi | 9 +++++++++
2 files changed, 16 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
index 759d1ec694b2..aadf9e4a8a05 100644
--- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
@@ -1,11 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
-#include "sa8775p-ride-r3.dts"
+#include "qcs9100-som.dtsi"
+
+#include "sa8775p-ride-common.dtsi"
+#include "sa8775p-ride-ethernet-aqr115c.dtsi"
+
/ {
model = "Qualcomm QCS9100 Ride Rev3";
- compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";
+ compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100-som", "qcom,qcs9100", "qcom,sa8775p";
};
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
new file mode 100644
index 000000000000..92adebb2e18f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
--
2.49.0
