Hello @Wysocki, Rafael J, @Moore, Robert, I've created a new PR on the ACPICA repository from the given Kernel patch: https://github.com/acpica/acpica/pull/1026 Could you please review this PR? Regards, Camacho Romero, Michal -----Original Message----- From: Wysocki, Rafael J <rafael.j.wysocki@xxxxxxxxx> Sent: Friday, May 16, 2025 10:41 PM To: Camacho Romero, Michal <michal.camacho.romero@xxxxxxxxx> Cc: linux-acpi@xxxxxxxxxxxxxxx; Mowka, Mateusz <mateusz.mowka@xxxxxxxxx>; Fedko, Artem <artem.fedko@xxxxxxxxx>; Pawlicki, AdamX <adamx.pawlicki@xxxxxxxxx>; Michalak, BartlomiejX <bartlomiejx.michalak@xxxxxxxxx>; acpica-devel@xxxxxxxxxxxxxxx; Moore, Robert <robert.moore@xxxxxxxxx>; Dumbre, Saket <saket.dumbre@xxxxxxxxx> Subject: Re: [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR On 5/16/2025 10:28 AM, Camacho Romero, Michal wrote: > > Hello @Moore, Robert <mailto:robert.moore@xxxxxxxxx>, @Wysocki, Rafael > J <mailto:rafael.j.wysocki@xxxxxxxxx> > > According to the latest version of the Intel TXT DMA Protection Ranges > specification > > (Revision 0.73), there were defined a new the ACPI Table, structure > and registers, which will be used to handle TPRs: > > * DTPR ACPI Table > > * TPR Base Register > > * TPR Serialize Request Register > > * TPR Limit Register > > * TPR Instance Structure > > * DMAR TXT Protected Reporting Structure > > Link: > https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Pr > otection_Ranges_rev_0p73.pdf > > Signed-off-by: Michal Camacho Romero michal.camacho.romero@xxxxxxxxx > Can you please submit this as a pull request to the upstream ACPICA project on GitHub? > --- > > include/acpi/actbl1.h | 86 +++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 86 insertions(+) > > diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h > > index 387fc821703a..14802feb54fd 100644 > > --- a/include/acpi/actbl1.h > > +++ b/include/acpi/actbl1.h > > @@ -47,6 +47,7 @@ > > #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer > table */ > > #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ > > #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics > Table */ > > +#define ACPI_SIG_DTPR "DTPR" /* TXT DMA Protection Ranges > reporting table */ > > #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ > > #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ > > @@ -1953,6 +1954,91 @@ struct acpi_ibft_target { > > u16 reverse_chap_secret_offset; > > }; > > +/******************************************************************************* > > + * > > + * DTPR - DMA TPR Reporting > > + * Version 1 > > + * > > + * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA > Protection > > + * Ranges", > > + * Revision 0.73, August 2021 > > + * > > + > ******************************************************************************/ > > + > > +struct acpi_table_dtpr { > > + struct acpi_table_header header; > > + u32 flags; // 36 > > +}; > > + > > +struct acpi_tpr_array { > > + u64 base; > > +}; > > + > > +struct acpi_dtpr_instance { > > + u32 flags; > > + u32 tpr_cnt; > > + struct acpi_tpr_array tpr_array[]; > > +}; > > + > > +/******************************************************************************* > > + * TPRn_BASE > > + * > > + * Specifies the start address of TPRn region. TPR region address and > size must > > + * be with 1MB resolution. These bits are compared with the result of the > > + * TPRn_LIMIT[63:20] * applied to the incoming address, to determine > if an > > + * access fall within the TPRn defined region. > > +*******************************************************************************/ > > +struct acpi_dtprn_base_reg { > > + u64 reserved0 : 3; > > + u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW) > > + u64 enable : 1; // 0 == range enabled, 1 == range disabled > > + u64 reserved1 : 15; > > + u64 tpr_base_rw : 44; // Minimal TPRn_Base resolution is 1MB. > > + // Applied to the incoming address, to determine if an > > + // access fall within the TPRn defined region. > > + // Width is determined by a bus width which can be > > + // obtainedvia CPUID function 0x80000008. > > + //u64 unused : 1; > > +}; > > + > > +/******************************************************************************* > > + * TPRn_LIMIT > > + * > > + * This register defines an isolated region of memory that can be enabled > > + * to prohibit certain system agents from accessing memory. When an agent > > + * sends a request upstream, whether snooped or not, a TPR prevents that > > + * transaction from changing the state of memory. > > +*******************************************************************************/ > > + > > +struct acpi_dtprn_limit_reg { > > + u64 reserved0 : 3; > > + u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW) > > + u64 enable : 1; // 0 == range enabled, 1 == range disabled > > + u64 reserved1 : 15; > > + u64 tpr_limit_rw : 44; // Minimal TPRn_Limit resolution is 1MB. > > + // These bits define TPR limit address. > > + // Width is determined by a bus width. > > + > > + //u64 unused : 1; > > +}; > > + > > +/******************************************************************************* > > + * SERIALIZE_REQUEST > > + * > > + * This register is used to request serialization of non-coherent DMA > > + * transactions. OS shall issue it before changing of TPR settings > > + * (base / size). > > +*******************************************************************************/ > > + > > +struct acpi_tpr_serialize_request { > > + u64 sts : 1; // Status of serialization request (RO) > > + // 0 == register idle, 1 == serialization in > progress > > + u64 ctrl : 1; // Control field to initiate serialization (RW) > > + // 0 == normal, 1 == initialize serialization > > + // (self-clear to allow multiple serialization requests) > > + u64 unused : 62; > > +}; > > + > > /* Reset to default packing */ > > #pragma pack() > > -- > > 2.43.0 > --------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. 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