On Fri, Aug 15, 2025, Peter Zijlstra wrote:
> On Wed, Aug 06, 2025 at 12:56:31PM -0700, Sean Christopherson wrote:
>
> > @@ -2727,6 +2739,21 @@ static struct pmu pmu = {
> > .filter = x86_pmu_filter,
> > };
> >
> > +void arch_perf_load_guest_context(unsigned long data)
> > +{
> > + u32 masked = data & APIC_LVT_MASKED;
> > +
> > + apic_write(APIC_LVTPC,
> > + APIC_DM_FIXED | PERF_GUEST_MEDIATED_PMI_VECTOR | masked);
> > + this_cpu_write(x86_guest_ctx_loaded, true);
> > +}
>
> I'm further confused, why would this ever be masked?
The idea is to match the guest's LVTPC state so that KVM doesn't trigger IRQ
VM-Exits on counter overflow when the guest's LVTPC is masked.
