On Wed, Jun 11, 2025 at 11:48:31AM +0100, Steven Price wrote:
> From: Jean-Philippe Brucker <jean-philippe@xxxxxxxxxx>
>
> The RMM describes the maximum number of BPs/WPs available to the guest
> in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1,
> which is visible to userspace. A VMM needs this information in order to
> set up realm parameters.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@xxxxxxxxxx>
> Signed-off-by: Steven Price <steven.price@xxxxxxx>
> Reviewed-by: Gavin Shan <gshan@xxxxxxxxxx>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
Reviewed-by: Joey Gouly <joey.gouly@xxxxxxx>
> ---
> arch/arm64/include/asm/kvm_rme.h | 2 ++
> arch/arm64/kvm/rme.c | 22 ++++++++++++++++++++++
> arch/arm64/kvm/sys_regs.c | 2 +-
> 3 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/kvm_rme.h b/arch/arm64/include/asm/kvm_rme.h
> index af5150c084ce..c8564d5aaff4 100644
> --- a/arch/arm64/include/asm/kvm_rme.h
> +++ b/arch/arm64/include/asm/kvm_rme.h
> @@ -94,6 +94,8 @@ void kvm_init_rme(void);
> u32 kvm_realm_ipa_limit(void);
> u32 kvm_realm_vgic_nr_lr(void);
>
> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
> +
> bool kvm_rme_supports_sve(void);
>
> int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap);
> diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c
> index 12cc34192b97..ce8e48ab8753 100644
> --- a/arch/arm64/kvm/rme.c
> +++ b/arch/arm64/kvm/rme.c
> @@ -87,6 +87,28 @@ u32 kvm_realm_vgic_nr_lr(void)
> return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_GICV3_NUM_LRS);
> }
>
> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
> +{
> + u32 bps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_BPS);
> + u32 wps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_WPS);
> + u32 ctx_cmps;
> +
> + if (!kvm_is_realm(vcpu->kvm))
> + return val;
> +
> + /* Ensure CTX_CMPs is still valid */
> + ctx_cmps = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val);
> + ctx_cmps = min(bps, ctx_cmps);
> +
> + val &= ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK |
> + ID_AA64DFR0_EL1_CTX_CMPs);
> + val |= FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) |
> + FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) |
> + FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps);
> +
> + return val;
> +}
> +
> static int get_start_level(struct realm *realm)
> {
> /*
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index da2d390ce9a5..b974eddfad53 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1847,7 +1847,7 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
> /* Hide BRBE from guests */
> val &= ~ID_AA64DFR0_EL1_BRBE_MASK;
>
> - return val;
> + return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val);
> }
>
> static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> --
> 2.43.0
>
