On Thu, Jul 10, 2025 at 02:46:11PM -0500, Babu Moger wrote: > Date: Thu, 10 Jul 2025 14:46:11 -0500 > From: Babu Moger <babu.moger@xxxxxxx> > Subject: [PATCH v2 2/2] target/i386: Add TSA feature flag verw-clear > X-Mailer: git-send-email 2.34.1 > > Transient Scheduler Attacks (TSA) are new speculative side channel attacks > related to the execution timing of instructions under specific > microarchitectural conditions. In some cases, an attacker may be able to > use this timing information to infer data from other contexts, resulting in > information leakage > > CPUID Fn8000_0021 EAX[5] (VERW_CLEAR). If this bit is 1, the memory form of > the VERW instruction may be used to help mitigate TSA. > > Link: https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf > Co-developed-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> > Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> > --- > v2: Split the patches into two. > Not adding the feature bit in CPU model now. Users can add the feature > bits by using the option "-cpu EPYC-Genoa,+verw-clear". > > v1: https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/ > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
