On 6/25/25 11:03 AM, Zhao Liu wrote:
On Tue, Jun 24, 2025 at 07:04:02PM +0800, Ewan Hai wrote:
Date: Tue, 24 Jun 2025 19:04:02 +0800
From: Ewan Hai <ewanhai-oc@xxxxxxxxxxx>
Subject: Re: [RFC 01/10] i386/cpu: Mark CPUID[0x80000005] as reserved for
Intel
On 6/24/25 3:22 PM, Zhao Liu wrote:
On Tue, May 27, 2025 at 05:56:07PM +0800, Ewan Hai wrote:
Date: Tue, 27 May 2025 17:56:07 +0800
From: Ewan Hai <ewanhai-oc@xxxxxxxxxxx>
Subject: Re: [RFC 01/10] i386/cpu: Mark CPUID[0x80000005] as reserved for
Intel
On 5/27/25 5:15 PM, Zhao Liu wrote:
On 4/23/25 7:46 PM, Zhao Liu wrote:
Per SDM, 0x80000005 leaf is reserved for Intel CPU, and its current
"assert" check blocks adding new cache model for non-AMD CPUs.
Therefore, check the vendor and encode this leaf as all-0 for Intel
CPU. And since Zhaoxin mostly follows Intel behavior, apply the vendor
check for Zhaoxin as well.
Note, for !vendor_cpuid_only case, non-AMD CPU would get the wrong
information, i.e., get AMD's cache model for Intel or Zhaoxin CPUs.
For this case, there is no need to tweak for non-AMD CPUs, because
vendor_cpuid_only has been turned on by default since PC machine v6.1.
Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
---
target/i386/cpu.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b64ceaaba46..8fdafa8aedaf 100644
[snip]>>> +
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
I've reviewed the cache-related CPUID path and noticed an oddity: every AMD
vCPU model still reports identical hard-coded values for the L1 ITLB and L1
DTLB fields in leaf 0x8000_0005. Your patch fixes this for Intel(and
Zhaoxin), but all AMD models continue to receive the same constants in
EAX/EBX.
Yes, TLB info is hardcoded here. Previously, Babu and Eduardo cleaned up
the cache info but didn't cover TLB [*]. I guess one reason would there
are very few use cases related to TLB's info, and people are more
concerned about the cache itself.
[*]: https://lore.kernel.org/qemu-devel/20180510204148.11687-2-babu.moger@xxxxxxx/
Understood. Keeping the L1 I/D-TLB fields hard-coded for every vCPU model is
acceptable.
Do you know the reason for this choice? Is the guest expected to ignore
those L1 TLB numbers? If so, I'll prepare a patch that adjusts only the
Zhaoxin defaults in leaf 0x8000_0005 like below, matching real YongFeng
behaviour in ecx and edx, but keep eax and ebx following AMD's behaviour.
This way is fine for me.
Thanks for confirming. I'll post the YongFeng cache-info series once your
refactor lands.
Hi Ewan,
By this patch:
https://lore.kernel.org/qemu-devel/20250620092734.1576677-14-zhao1.liu@xxxxxxxxx/
I fixed the 0x80000005 leaf for Intel and Zhaoxin based on your feedback
by the way.
It looks like the unified cache_info would be very compatible with
various vendor needs and corner cases. So I'll respin this series based
on that cache_info series.
Before sending the patch, I was thinking that maybe I could help you
rebase and include your Yongfeng cache model patch you added into my v2
series, or you could rebase and send it yourself afterward. Which way do
you like?
It would be great if you could include the Yongfeng cache-model patch in
your v2 series. Let me know if you need any more information about the
Yongfeng cache model. After you submit v2, I can review the Zhaoxin parts
and make any necessary code changes if needed.
And thanks again for taking Zhaoxin into account.
Welcome; it's something I can easily help with. If possible, when v2 is
out, hope you could help test it on your platform to ensure everything
is fine. :-) And I've verified it myself through TCG.
There's no problem!> Thanks,
Zhao
